Ruprecht-Karls-Universität Heidelberg


SEED – Support for Education in Electronic Design

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SEED is a university/industry collaboration to enhance and reform the education in the field of semi-custom/full-custom ASIC design at the Universities of Mannheim, Heidelberg and Kaiserslautern, Germany. With this project Cadence Design Systems enables us to teach leading-edge ASIC design using their most innovative products.

At the Computer Architecture Group, University of Mannheim, SEED was the base foundation to create the lecture and practical course 'Semi-Custom Design Flow' (SCDF), where our students learn the methodology of high-speed nanometer ASIC design by the use of the most innovative EDA tools. This lecture and practical course affiliates perfectly to the lecture 'hardware design', that has been held for years now and covers (architectural) system, interface and digital circuit design using Verilog HDL.

Like the afore mentioned lecture and practical course 'Semi-Custom Design Flow' all participating universities introduced new lectures and courses. Also existing courses have been restructured in a way that the whole design flow is covered both in theory and practice. The main focus during this work is to develop practical exercises suitable for student work but also complex enough to face the problems of real-world designs. Missing tool experience is compensated by experts from Cadence VCAD Services in Feldkirchen, Germany.

The expertise of the participating groups define the advanced subject course curriculum. It ranges from the afore mentioned:

  • high-level system and interface design,
  • synthesis, place and route, extraction, static timing analysis (the whole cell-based design flow),
  • to full custom analog and standard cell design and
  • the integration of both worlds by timing, power and functional characterization and abstract generation.

By virtually integrating Cadence engineers into our Computer Aided Design ("CAD") activities, we will benefit not only from the experience of the specific engineers, but also from a direct channel to Cadence's know-how network. This will typically result in a more reliable design environment designed for flexibility and also in a faster and smoother integration of technology enhancements. For us, this will provide the possibility of designing higher quality designs, within shorter design cycles.

The SEED project was initiated in 2002 by the Computer Architecture Group, University of Mannheim.

In order to optimize University Education in close collaboration to industry, we hosted the first Cadence Academic Network (CAN) Day in 2006.

For further information contact Patrick Haspel at Cadence: phaspel {at} cadence.com or
David Slogsnat
at the University of Heidelberg.

Images

Oase Chip

Oase Chip                         

  • 5 x 2,17 mm² die area
  • 2.5 GHz PLL, serializer and CML I/Os
  • TRAP2 bonding compatibility to allow chip-to-chip bonding

Trap2 Chip

Trap2 Chip

 

  • taped out May 2003 via IMEC for UMC´s mixed-signal 0.18µ CMOS
  • 5 x 7,4 mm² die area, 5 custom memory blocks, 167 MHz
  • 23 low power ADCs, temperature sensor

 

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