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What is openHMC ?

openHMC is an open-source project developed by the Computer Architecture Group (CAG) at the University of Heidelberg in Germany. It is a configurable, vendor-agnostic, AXI-4 compliant Hybrid Memory Cube (HMC) controller that can be parameterized to different data-widths, external lane-width requirements, and clock speeds depending on speed and area requirements. It further includes a test environment to evaluate the capabilities of the openHMC controller.

The main objective of developing the HMC controller is to lower the barrier for others to experiment with the HMC, without the risks of using commercial solutions. This project is licensed under the terms and conditions of version 3 of the Lesser General Public License.

Find out more about the Hybrid Memory Cube

 

The openHMC Controller

The openHMC controller is presented as a high-level block diagram in the figure below. The asynchronous input and output FIFOs allow the user to access the memory controller from a different clock domain. On the transceiver side, a registered output holds the data reordered on a lane-by-lane basis; allowing seamless integration with any transceiver types. A register-file provides access to control and monitor the operation of the memory controller.

 

Features

The openHMC controller implements the following features as described in the HMC specification Rev 1.1:

  • Full link-training, sleep mode, and link retraining 
  • 16Byte up to 128Byte read and write (posted and non-posted) transactions
  • Posted and non-posted bit-write and atomic requests
  • Mode Read and Write
  • Full packet flow control
  • Packet integrity checks (sequence number, packet length, CRC,...)
  • Full automatic link retry

Supported Configurations

Currently the following configurations are supported (8 or 16 lanes):

    • 2 FLITs per Word / 256-bit datapath
    • 4 FLITs per Word / 512-bit datapath
    • 6 FLITs per Word / 768-bit datapath
    • 8 FLITs per Word / 1024-bit datapath
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