Ruprecht-Karls-Universität Heidelberg


Master Thesis

 Author  Title  Supervisor
 Tobias Groschup  Implementation and Evaluation of a Parallel Distributed File System
 for the EXTOLL High-Performance Network
 Sarah Neuwirth
 Alexander Jäger  Exploration and Evaluation of State of the Art Interfaces used in FPGAs
 Juri Schmidt
 Stefan Kosnac  Design Aspects of a Decision Feedback Equalizer in a 28nm Technology
 Markus Mueller
 Max Thuermer
 Daniel Kruck  Simulating and Analyzing the Extoll Network with a Timing-Accurate
 SystemC Model
 Niels Burkhardt
 Michael Magin  Signal and Power Analysis of a High Performance ASIC Package  Markus Mueller
 Tobias Markus  High-Speed Clock Generation Architecture for a Multi-Rate
 SerDes in 28nm
 Markus Mueller
 Philipp Schäfer  Design and Implementation of a Prototype ASIC for a Unified DAQ
 Interconnection Network
 Frank Lemke
 Juri Schmidt  A Hybrid Memory Cube Controller for FPGAs  Myles Watson
 Felix Zahn  Development of a Flexible Management Software Environment for the
 EXTOLL Network
 Richard Leys

 

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