Ruprecht-Karls-Universität Heidelberg


Diploma Thesis

 Author  Title  Supervisor
 Alexander Giese

 Development and Verification of a HyperTransport-Interface     
 with Optimizations for FPGA Environments

 David Slogsnat
 Alexandra Bernhardt  

 Design, Implementation and Synthesis of a Parameterizable
 Soft IP Cell for a high performance crossbar

 Patrick R. Schulz
 Andreas Peters

 Evaluation, Optimization and Verification of a 10Gbit Ethernet MAC

 Christian Leber
 Benjamin Geib
 Anton Klotz

 Design Methodology for Engineering Change Orders (ECOs)
 in a Flat Physical Design Environment

  • Abstract (not available)
 Patrick R. Schulz
 Benjamin Bruno

 Konzeption und Prototypen-Implementierung einer Software zum
 effizienten Entwurf von Hardware mit Hilfe einer hierarchischen
 Methodik

  • Abstract
 Frank Lemke
 Benjamin Geib

 Improving and Extending a Crossbar Design
 for ASIC and FPGA Implementation

 David Slogsnat

 Benjamin Kalisch

 

 Design and Implementation of a HyperTransport I/O-Link
 Controller complying with Specification 3.0

 Alexander Giese
 Boris Strohmeier

 Design and implementation of a high speed serializing multi-
 purpose interconnect with improved testability as a key aspect

 Holger Froening
 Christian Leber

 A hardware-oriented simulator for high performance inter-
 connection network architectures

Mondrian Nuessle
 Christian Leibig

 FPGA-based Implementation of Alternative Memory
 Consistency Models

 Sven Kapferer
 Daniel Bayer

 Development of an Automated Verification Environment

 Sven Kapferer
 David Slogsnat

 Simulation and Architectural Exploration of a Shared-Memory
 Multiprocessor Node for Scientific Algorithms

 Patrick R. Schulz
 Dirk Franger

 A Multi-Context Engine for Remote Memory Access
 to Improve System Area Networking

  • Abstract (not available)
 Holger Froening
 Dirk Frey

 Verification and Implementation of PCI Express Endpoint
 Remote Configuration using EXTOLL

 Benjamin Kalisch
 Elmar Greulich

 System Design of an HT3 Verification Platform
 based on a high-performance FPGA

 Frank Lemke
 Erdin Sinanovic

 Design and Implementation of a Multicast
 Communication Hardware Structure

 Benjamin Geib
 Felix Rembor

 Exploration, Development and Implementation
 of different TLB Functions and Mechanisms

 Holger Froening
 Frank Lemke

 FSMDesigner4 - Development of a Tool for
 Interactive Design and Hardware Description Language
 Generation of Finite State Machines

 Mondrian Nuessle
 Frank Ueltzhoeffer

 Design and Implementation of a Virtual Channel
 Based Low-Latency Crossbar Switch

 Patrick R. Haspel
 & Ulrich Bruening
 Goetz Becker
  • Abstract (not available)
 David Slogsnat
 Heiner Litz

 Advanced Hardware Communication Techniques

 Holger Froening
 Holger Bellm  Architectural Design and Prototype Implementation
 of an Embedded Network Processor Core with Language
 for Instruction Set Architectures (LISA)
  • Abstract (not available)
 Patrick R. Schulz
 Holger Froening  Design, Simulation and Implementation of an Interconnect
 including a Printed Circuit Board and Chip Package for High
 Speed Signals with improved Signal Integrity
 Ulrich Bruening
 Holger Sattel  A Scalable Generic Simulator - SWORDFISH
 (Simple Wormhole Routing and Fault Injection
 on Simulated Hardware)
  Mondrian Nuessle
 Ingo Feldner  High-level Executable Specification Development
 of a High Performance System Area Network Chip
  Patrick R. Haspel
 Jan Seyler  A Graphical Guided Testbench Creation Tool for
 Functional Hardware Verification based on UVM
  • Abstract (not available)
 Niels Burkhardt
 Janusz Schinke

 Design and Verification of a Low Latency Funtional
 Unit for Direct Access to Remote Memory

 Holger Froening
 Jochen Kinzel   Design, Implementation and Verification of a High
 Performance NAND Flash Based Storage System
 with HyperTransport Interface
 Christian Leber
 Johannes Kohlmann  Design of a Chip and Modul Testing Environment  Ulrich Bruening
 Kilian Polyak  GPUNAA - Network-Attached Accelerators Architecture with GPGPUs
  • Abstract (not available)

 Dirk Frey &
 Sarah Neuwirth

 Markus Mueller

 Exploring the Testability Methodology and the Development
 of Test and Debug Functions for a Complex Network ASIC

 Sven Kapferer
 Martin Scherer  Implementation, Synthesis and Verification
 of a Remote Shared Memory Access Functional Unit
 Mondrian Nuessle
Martin Tschischauskas  Metric Driven and Formal Verification: A Survey
 Niels Burkhardt
 Mathias Kunst  A Unified Multi Context Networking Engine  Mondrian Nuessle
 Matthaeus Peterson  Design and Implementation of Enhanced Features
 for FSMDesigner 4 with Complex HDL Generation Options
 Frank Lemke
 Matthias Harter  Quality Analysis of back-end tools in a cell-based design flow
 of a high-performance multi-million gate ASIC
 Patrick R. Schulz
 Matthias Scheerer  Definition and Implementation of a Hardware Abstraction Layer
 (HAL) for an ASIC-Prototyping Station using a 64Bit/66MHz PCI
 interfaced FPGA
 Patrick R. Schulz
 Maximilian Thuermer Design and Implementation of an HT3 Electrical Interface
  • Abstract (not available)
 Heiner Litz
 Michael Riemer  Development of a Verification Environment based on the Open
 Verification Methodology for the EXTOLL Interconnection Network
 Niels Burkhardt
 Mondrian Nuessle  Design and Implementation of a distributed management system
 for the ATOLL high-performance network
 Holger Froening
 Niels Burkhardt

 Fast Hardware Barrier Synchronisation for a Reliable Inter-
 connection Network

 David Slogsnat
 Patrick Schulz  Design for Test (DFT) and Testability of a Multi-Million Gate ASIC    
 Ulrich Bruening
 Phillip Degler  Software Stack of a High Performance Interconnection Network  Mondrian Nuessle
 Richard Sohnius  Creating an Executable Specification Using SystemC of a High
 Performance, Low Latency Multilevel Network Router
 Patrick R. Haspel
 Sarah Neuwirth  Block Oriented Cache Layer for High Speed Flash
 Christian Leber
 Sebastian Ivars  FPGA-based Prototyping Environment for Network Interfaces  David Slogsnat
 Steffen Kurz  A Management System for the EXTOLL Network
 Mondrian Nuessle
 Stephan Walter  On-Chip Measurement Units for High-Speed Signals
 Markus Mueller
 Max Thuermer
 Sven Kapferer  Design Space Analysis and Implementation
 of a Cache Coherent Device for HyperTransport
 David Slogsnat
 Sven Schenk  Architecture Analysis of Multi-Gigabit-Transceivers
 for Low Latency Communication
 Heiner Litz
 Sven Stork  Design of an efficient Software Environment
 for a RDMA Network Interface Controller
 Mondrian Nuessle
 Thomas Schlichter  Exploration of Hard- and Software Requirements for one-sided,
 zero copy user level Communication and its Implementation
  • Abstract (not available)
 Ulrich Bruening
 Timo Reubold  Design, Implementation and Verification of a PCI Express to
 HyperTransport Protocol Bridge
 Christian Leber
 Timo Sponer  Development, Verification and Integration of a Processing Unit
 in the Communication Function of a SAN Device in SystemC
  • Abstract (not available)
 Patrick R. Haspel
 Tobias Hettinger  Design and Implementation of Efficient and Reliable Network
 Protocols for the ATOLL System Area Network
  • Abstract (not available)
 David Slogsnat
 Tobias Jakob  Multilevel Optimization of Parallel Applications Utilizing
 a System Area Network
 Markus Fischer
 Tobias Kienzle

 Message-Passing Layer for the EXTOLL High-Performance
 Interconnection Network

 Mondrian Nuessle

 

 

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