Ruprecht-Karls-Universität Heidelberg


Diploma Thesis

  • Alexander Giese (Supervisor: David Slogsnat)
    Development and Verification of a HyperTransport-Interface with Optimizations for FPGA Environments [Abstract]
  • Alexandra Bernhardt (Supervisor: Patrick R. Schulz)
    Design, Implementation and Synthesis of a Parameterizable Soft IP Cell for a high performance crossbar [Abstract]
  • Andreas Peters (Supervisor: Christian Leber, Benjamin Geib)
    Evaluation, Optimization and Verification of a 10Gbit Ethernet MAC [Abstract]
  • Anton Klotz (Supervisor: Patrick R. Schulz)
    Design Methodology for Engineering Change Orders (ECOs) in a Flat Physical Design Environment [Abstract]
  • Benjamin Bruno (Supervisor: Frank Lemke)
    Konzeption und Prototypen-Implementierung einer Software zum effizienten Entwurf von Hardware mit Hilfe einer hierarchischen Methodik [Abstract]
  • Benjamin Geib (Supervisor: David Slogsnat)
    Improving and Extending a Crossbar Design for ASIC and FPGA Implementation [Abstract]
  • Benjamin Kalisch (Supervisor: Alexander Giese)
    Design and Implementation of a HyperTransport I/O-Link Controller complying with Specification 3.0 [Abstract]
  • Boris Strohmeier (Supervisor: Holger Fröning)
    Design and implementation of a high speed serializing multi-purpose interconnect with improved testability as a key aspect [Abstract]
  • Christian Leber (Supervisor: Mondrian Nüßle)
    A hardware-oriented simulator for high performance interconnection network architectures [Abstract]
  • Christian Leibig (Supervisor: Sven Kapferer)
    FPGA-based Implementation of Alternative Memory Consistency Models [Abstract]
  • Daniel Bayer (Supervisor: Sven Kapferer)
    Development of an Automated Verification Environment [Abstract]
  • David Slogsnat (Supervisor: Patrick R. Schulz)
    Simulation and Architectural Exploration of a Shared-Memory Multiprocessor Node for Scientific Algorithms [Abstract]
  • Dirk Franger (Supervisor: Holger Fröning)
    A Multi-Context Engine for Remote Memory Access to Improve System Area Networking [Abstract ]
  • Dirk Frey (Supervisor: Benjamin Kalisch)
    Verification and Implementation of PCI Express Endpoint Remote Configuration using EXTOLL [Abstract]
  • Elmar Greulich (Supervisor: Frank Lemke)
    System Design of an HT3 Verification Platform based on a high-performance FPGA [Abstract]
  • Erdin Sinanovic (Supervisor: Benjamin Geib)
    Design and Implementation of a Multicast Communication Hardware Structure [Abstract]
  • Felix Rembor (Supervisor: Holger Fröning)
    Exploration, Development and Implementation of different TLB Functions and Mechanisms [Abstract]
  • Frank Lemke (Supervisor: Mondrian Nüßle)
    FSMDesigner4 - Development of a Tool for Interactive Design and Hardware Description Language Generation of Finite State Machines [Abstract]
  • Frank Ultzhöffer (Supervisor: Patrick R. Haspel, Ulrich Brüning)
    Design and Implementation of a Virtual Channel Based Low-Latency Crossbar Switch [Abstract]
  • Götz Becker (Supervisor: David Slogsnat)
    - Title not available - [Abstract]
  • Heiner Litz (Supervisor: Holger Fröning)
    Advanced Hardware Communication Techniques [Abstract]
  • Holger Belim (Supervisor: Patrick R. Schulz)
    Architectural Design and Prototype Implementation of an Embedded Network Processor Core with Language for Instruction Set Architectures (LISA) [Abstract]
  • Holger Fröning (Supervisor: Ulrich Brüning)
    Design, Simulation and Implementation of an Interconnect including a Printed Circuit Board and Chip Package for High Speed Signals with improved Signal Integrity [Abstract]
  • Holger Sattel (Supervisor: Mondrian Nüßle)
    A Scalable Generic Simulator - SWORDFISH (Simple Wormhole Routing and Fault Injection on Simulated Hardware) [Abstract]
  • Ingo Feldner (Supervisor: Patrick R. Haspel)
    High-level Executable Specification Development of a High Performance System Area Network Chip [Abstract]
  • Jan Seyler (Supervisor: Niels Burkhardt)
    A Graphical Guided Testbench Creation Tool for Functional Hardware Verification based on UVM [Abstract]
  • Janusz Schinke (Supervisor: Holger Fröning)
    Design and Verification of a Low Latency Funtional Unit for Direct Access to Remote Memory [Abstract]
  • Jochen Kinzel (Supervisor: Christian Leber)
    Design, Implementation and Verification of a High Performance NAND Flash Based Storage System with HyperTransport Interface [Abstract]
  • Johannes Kohlmann (Supervisor: Ulrich Brüning)
    Design of a Chip and Modul Testing Environment [Abstract]
  • Kilian Polyak (Supervisor: Dirk Frey, Sarah Neuwirth)
    GPUNAA - Network-Attached Accelerators Architecture with GPGPUs [Abstract]
  • Markus Müller (Supervisor: Sven Kapferer)
    Exploring the Testability Methodology and the Development of Test and Debug Functions for a Complex Network ASIC [Abstract]
  • Martin Scherer (Supervisor: Mondrian Nüßle)
    Implementation, Synthesis and Verification of a Remote Shared Memory Access Functional Unit [Abstract]
  • Martin Tschischauskas (Supervisor: Niels Burkhardt)
    Metric Driven and Formal Verification: A Survey [Abstract]
  • Mathis Kunst (Supervisor: Mondrian Nüßle)
    A Unified Multi Context Networking Engine [Abstract]
  • Matthaeus Peterson (Supervisor: Frank Lemke)
    Design and Implementation of Enhanced Features for FSMDesigner 4 with Complex HDL Generation Options [Abstract]
  • Matthias Harter (Supervisor: Patrick R. Schulz)
    Quality Analysis of back-end tools in a cell-based design flow of a high-performance multi-million gate ASIC [Abstract]
  • Matthias Scheerer (Supervisor: Patrick R. Schulz)
    Definition and Implementation of a Hardware Abstraction Layer (HAL) for an ASIC-Prototyping Station using a 64Bit/66MHz PCI interfaced FPGA [Abstract]
  • Maximilian Thürmer (Supervisor: Heiner Litz)
    Design and Implementation of an HT3 Electrical Interface [Abstract]
  • Michael Riemer (Supervisor: Niels Burkhardt)
    Development of a Verification Environment based on the Open Verification Methodology for the EXTOLL Interconnection Network [Abstract]
  • Mondrian Nüßle (Supervisor: Holger Fröning)
    Design and Implementation of a distributed management system for the ATOLL high-performance network [Abstract]
  • Niels Burkhardt (Supervisor: David Slogsnat)
    Fast Hardware Barrier Synchronisation for a Reliable Interconnection Network [Abstract]
  • Patrick R. Schulz (Supervisor: Ulrich Brüning)
    Design for Test (DFT) and Testability of a Multi-Million Gate ASIC [Abstract]
  • Philip Degler (Supervisor: Mondrian Nüßle)
    Software Stack of a High Performance Interconnection Network [Abstract]
  • Richard Sohnius (Supervisor: Patrick R. Haspel)
    Creating an Executable Specification Using SystemC of a High Performance, Low Latency Multilevel Network Router [Abstract]
  • Sarah Neuwirth (Supervisor: Christian Leber)
    Block Oriented Cache Layer for High Speed Flash [Abstract]
  • Sebastian Ivars (Supervisor: David Slogsnat)
    FPGA-based Prototyping Environment for Network Interfaces [Abstract]
  • Steffen Kurz (Supervisor: Mondrian Nüßle)
    A Management System for the EXTOLL Network [Abstract]
  • Stephan Walter (Supervisor: Markus Müller, Maximilian Thürmer)
    On-Chip Measurement Units for High-Speed Signals [Abstract]
  • Sven Kapferer (Supervisor: David Slogsnat)
    Design Space Analysis and Implementation of a Cache Coherent Device for HyperTransport [Abstract]
  • Sven Schenk (Supervisor: Heiner Litz)
    Architecture Analysis of Multi-Gigabit-Transceivers for Low Latency Communication [Abstract]
  • Sven Stork (Supervisor: Mondrian Nüßle)
    Design of an efficient Software Environment for a RDMA Network Interface Controller [Abstract]
  • Thomas Schlichter (Supervisor: Ulrich Brüning)
    Exploration of Hard- and Software Requirements for one-sided, zero copy user level Communication and its Implementation [Abstract]
  • Timo Reubold (Supervisor: Christian Leber)
    Design, Implementation and Verification of a PCI Express to HyperTransport Protocol Bridge [Abstract]
  • Timo Sponer (Supervisor: Patrick R. Haspel)
    Development, Verification and Integration of a Processing Unit in the Communication Function of a SAN Device in SystemC [Abstract]
  • Tobias Hettinger (Supervisor: David Slogsnat)
    Design and Implementation of Efficient and Reliable Network Protocols for the ATOLL System Area Network [Abstract]
  • Tobias Jakob (Supervisor: Markus Fischer)
    Multilevel Optimization of Parallel Applications Utilizing a System Area Network [Abstract]
  • Tobias Kienzle (Supervisor: Mondrian Nüßle)
    Message-Passing Layer for the EXTOLL High-Performance Interconnection Network [Abstract]
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