University of Heidelberg Institute of Computer Engineering


Downloads

The HT-Core is an open core development and is available here as Verilog HDL source code.

Description of the files:

HT-Example-Design Version 1.00 for the HTX-Board:
  • The ht_example_design_1.00.tar.gz contains a HTX-Board specific design.
  • In the subfolder bitfiles the programming files for FX60 and FX100 can be found.
  • In the subfolder docu the documentation files can be found.
  • In the subfolder hdl the hardware description language files of the HT-Core can be found.
  • In the subfolder include the header files can be found.
  • In the subfolder license the license files can be found.
  • In the subfolder software the example-device drivers and software files can be found.
  • In the subfolder ucf the HTX-Board specific ucf file can be found.

  • The design is a minimum implementation of the HT-Core. It runs with a 16 bit wide link at a link frequency of HT200. Note that a change of the htcore_params.h file will cause a failure of the design.
HT-Core Version 1.00 platform ports:
  • Xilinx

    • The xilinx_1.00.tar.gz contains the XILINX specific design.
    • In the subfolder ht_16_cave the platform independent files can be found.
    • In the subfolder xc4v the platform specific files are placed.
    • The subfolder includes contains the header file.

    Note that a change of the htcore_params.h file may cause a failure of the design.

  • Lattice

    • The lattice_1.00.tar.gz contains the LATTICE specific design.
    • In the subfolder ht_16_cave the platform independent files can be found.
    • In the subfolder lattice_scm80 the platform specific files are placed.
    • The subfolder includes contains the header file.

    Note that a change of the htcore_params.h file may cause a failure of the design.

  • Altera

    • The altera_1.00.tar.gz contains the ALTERA specific design.
    • In the subfolder ht_16_cave the platform independent files can be found.
    • In the subfolder ep2s90 the platform specific files are placed.
    • The subfolder includes contains the header file.

    Note that a change of the htcore_params.h file may cause a failure of the design.

    Files generated with the Quartus Mega Wizard Plug-In contain a copyright and cannot be provided for download. Therefore snapshots from the generation of these files were taken to be able to recreate them. The snapshots can be found in the ep2s90 folder.

    After creating the fifo_dc_3x10_stratixii.v FIFO the same flow must be repeated for the following files just with changes of the width and depth parameters.
    • fifo_dc_40x4_stratixii.v Width 40 Depth 16
    • fifo_dc_64x8_stratixii.v Width 64 Depth 256
    • fifo_dc_6x8_stratixii.v Width 8 Depth 256
    • fifo_dc_7x7_stratixii.v Width 7 Depth 128
    • fifo_dc_96x5_stratixii.v Width 96 Depth 32

    • fifo_sc_3x10_stratixii.v Width 3 Depth 1024
    • fifo_sc_40x4_stratixii.v Width 40 Depth 16
    • fifo_sc_64x8_stratixii.v Width 64 Depth 256
    • fifo_sc_6x8_stratixii.v Width 8 Depth 256
    • fifo_sc_7x7_stratixii.v Width 7 Depth 128
    • fifo_sc_96x5_stratixii.v Width 96 Depth 32

The file ht_bundle_0.90.tar.gz contains all files which can be downloaded afterwards separately. It includes
  • ht_core (Verilog source code for the 8 bit core with 200MHz link speed and LDTSTOP functionality, user maual and include files)
  • ht_documentation
  • ht_example_device
  • ht_example_programming
  • ht_example_software
  • ht_example_testbench

The file ht16_bundle_0.90.tar.gz contains all files which can be downloaded afterwards separately. It includes
  • ht16_core (Verilog source code for the 16 bit core with 200MHz link speed and LDTSTOP functionality, user maual and include files)
  • ht16_documentation
  • ht16_example_device
  • ht16_example_programming
  • ht16_example_software
  • ht16_example_testbench

License Notice:
The use of the HT core requires membership in the HT consortium. For more details, see www.hypertransport.org.

The cHT core is only available under the coherent HyperTransportTM License from AMD. Please contact AMD for further details of licensing and delivery of the core.



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Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: coeht{at}ziti.uni-heidelberg.de

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