University of Heidelberg Institute of Computer Engineering


Frequently Asked Questions

  • Q: Who developed the HT-Core?
    A: The HT-Core was developed by the Computer Architecture Group.

  • Q: Why is there sometimes University of Mannheim (UoM) and sometimes Universit of Heidelberg (UoH) named?
    A: The HT-Core was developed while the Computer Architecture Group was part of the UoM. Since 1th of January 2008, the CAG is affiliated to the UoH. The Computer Engineering Department including the CAG was swapped to the University of Heidelberg (UoH) but all groups are staying in the known building B6 in Mannheim. New University name, old location :-).

  • Q: When and how will the HT-Core be made available?
    A: The HT-Core (8/16bit version with HT200) can be downloaded from our web page. The faster version with HT400 will be released very soon, depending on the porting and optimization progress. If you do not want to miss the release date, subscribe to our newsletter!

  • Q: What will the pricing options look like?
    A: This HT-Core itsself is free of charge. However, users will be obligated to secure a HyperTransport technology license from the HyperTransport Technology Consortium if and by the time any of the party's products based on the HT-Core is openly promoted or sold.

  • Q: How can I get the coherent HT core?
    A: The coherent HT-Core (cHT core) contains specific informations on the coherence protocol of AMDs processors. Therefore we do not deliver the cHT core on our download page. You must have a special coherent HT license from AMD to be allowed to look into the core. If you have aquired such a license from AMD you will get the cHT core from your AMD NDA download area.

  • Q: What does HT400 stand for?
    A: HyperTransport supports a variety of link clock frequencies. HTxxx usually specifies the (maximum) link clock frequency a device supports. This notation is not defined officially in the HT spec, however, it is widely used. The transfer rate for data is doubled due to the double data rate (DDR) mode of HT.

  • Q: How many FPGA ressources will the HT-Core use?
    A: The number of resources for the various FPGA technologies will be stated at the vendor specific pages. The HT core is carefully designed to fit into FPGAs at reasonable speed leaving sufficient space for additional user logic.

  • Q: What platforms are currently supported for the HT-Core?
    A: The HT-Core has been optimzed for and ported to the main FPGA vendor platforms.

  • Q: Will the HT-Core also work on other platforms?
    A: Most of it is plain Verilog RTL, only a small part is device specific code. Thus, you can port the HT-Core to other FPGAs or even ASIC designs yourself. However, you should have an excellent knowledge about your target platform. We currently provide support for platforms from Xilinx, Altera and Lattice.

  • Q: Can you help us implementing the HT-Core in an ASIC?
    A: The Computer Architecture Group has done a number of ASIC implementations in the past. We are currently working on an ASIC implementation and will report on this activity as soon as it is completed.

  • Q: What FPGA-hardware solutions can be used with the HT-Core?
    A: The HTX-Board of the Computer Architecture Group, University of Heidelberg, has been verified to work with the HT-Core. This is also the hardware that we use ourselves in a production environment. As the HT-Core adheres to the HTX and HT specifications, it should also work with any other solution that is fully compliant to HTX and HT specifications.

  • Q: Which motherboard can you recommend for use with the HT-Core?
    A: We have verified the Iwill DK8-HTX board to work properly with the HTX board and the HT-Core. This Iwill board must be equipped with Linux-BIOS to support HTX devices properly. LinuxBIOSv2 r2481 has been verified, newer versions should also work. A HOWTO describing how you have to configure LinuxBIOS properly can be obtained by contacting us. In the meantime we have verified more motherboards with the HTX conncetor, e.g. the DL145G3 from HP.


Last modified: 02.05.2011

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Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: coeht{at}ziti.uni-heidelberg.de

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