The focus of research projects of the CoEHT is located in the area of high performance IP design. We focus on the development of IP cores for our HT rapid prototyping station without restricting the designs to FPGA applications. These IPs are building blocks to connect application IPs over HyperTransport to other HyperTransport (HT) devices, e.g. over the HTX connector to an AMD Opteron processor.

The HT connection compared to other available peripheral interconnects is a direct connection without any intermediate devices or protocol conversions. The device itself uses the same protocol as the main processor of the system. HT is a very lean protocol which allows lowest possible latencies including all accesses, achieved through very low protocol overhead and a direct connection between the CPU and the device respectively device and main memory.