University of Heidelberg Institute of Computer Engineering


The HT-Core provides an efficient way to build user specific devices by mapping the core and device modules to a programmable logic device connected to the HyperTransport Link. It provides a comfortable and efficient way to evaluate user specific devices connected to the HyperTransport connector standardized under the name HTX-Connector. It can be used in conjuction with the HTX-Board (see HTX-Board data sheet).

The HT-Core is a non-coherent HyperTransport cave device. A cave is an endpoint device in a HyperTransport chain. The core is a low latency device with a queue based application interface. Three queues are provided in each direction (see also block diagram):
  • posted queue
  • non-posted queue
  • response queue
The HT400 interface delivers 3,2 GByte/s bidirectional bandwidth and a very low latency


  • Very low latency device access
  • suitable to connect a device to any AMD Opteron. processor node via a HTX connector
  • up to 3,2GByte/s bidirectional bandwidth via an HT400 interface on FPGAs
  • Configurable data width of max. 16bit bidirectional interface
  • Max. internal clock frequency of 200MHz on FPGAs
  • Internal data path width of 4x the link width (32/64bits)
  • Convenient device interface at end of queues
  • HyperTransport interface is implemented for Xilinx serializing IO cells
  • Programmable core logic for the Xilinx Virtex-4 FPGA series and Altera Stratix 2 series
  • Uses minimal hardware resources
  • Fully synchronous design
  • Efficient pipelined structure
  • Synthesizable Verilog HDL code

Scope of delivery

  • Verilog source code for mapping to Xilinx Virtex4 FX series FPGAs. Verified on the HTX-Board Computing evironment: Iwill DK8-HTX mainboard with LINUX-BIOS and HTX board.
    A constraint file in Xilinx .ucf file format describing the pinout is included.
  • Verilog source for Altera Stratix 2 based platform is currently available on request only.

Currently Supported Platforms

  • The HTX-Board of the Computer Architecture Group at the Department of Computer Engineering, University of Mannheim.
  • An Altera-based platform is to be supported soon.

Block diagram

HT-Core Users


The HT-Core is available under an open source license to any interested party. The acquiring party will be obligated to secure a HyperTransport technology license if and by the time any of the party's products based on the HT-Core is openly promoted or sold. A royalty-free HyperTransport technology license can be acquired by simply becoming a member of the HyperTransport Technology Consortium. Complete information about HyperTransport Consortium membership classes, benefits, fees and application guidelines can be found here.

Last modified: 02.02.2018

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Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: coeht{at}


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