University of Heidelberg Institute of Computer Engineering




HT-Core Altera Stratix port

The Computer Architecture Group (CAG) is proud to announce the availability of the HT-Core for Altera Stratix II devices. The core implements a complete 16-bit HyperTransport cave device and can be mapped onto an Altera Stratix II FPGA. The HT-Core is released under an open-source license.

Porting of the Core to the Altera architecture involved adapting clocking, input/output and FIFO ressources to Altera specific macros/primitives. This involved effective use of LVDS, PLL and FIFO MegaFunctions from within the Altera design software. The rest of the Core is written in architecture agnostic HDL code and cleanly implemented using the Quartus II 7.2 software from Altera.

The resulting image has successfully been loaded onto a Stratix II device. The HTX-based 10 Gigabit Ethernet Board Reference Design equipped with an EP2S90F1020C4 device has been used to prove functionality of the Core in a real system. Both an Iwill DK8-HTX based system and an HP DL145G3 machine have been used to test the core.

The current release of the HT-Core includes the version for Altera FPGAs as well as an example design. It is available for download from the CoEHT download page.

Description

The HT-Core provides an efficient way to build user specific devices by mapping the core and device modules to a programmable logic device connected to the HyperTransport Link. It provides a comfortable and efficient way to evaluate user specific devices connected to the HyperTransport connector standardized under the name HTX-Connector.

The HT-Core is a non-coherent HyperTransport cave device. A cave is an endpoint device in a HyperTransport chain. The core is a low latency device with a queue based application interface. Three queues are provided in each direction:
  • posted queue
  • non-posted queue
  • response queue
The Altera version currently supports an HT200 interface with 1.6 GByte/s of bidirectional bandwidth and a very low latency of 300 ns (PIO Read).

Scope of delivery

  • Verilog source code for mapping to Altera series FPGAs. Verified on the HTX-Board Computing evironment: Iwill DK8-HTX mainboard and HTX-based 10 Gigabit Ethernet Board Reference Design. Also a HP DL145G3 machine has been used to test the device.
    A file describing the pinout is included.

Board Image

License

The HT-Core is available under an open source license to any interested party. The acquiring party will be obligated to secure a HyperTransport technology license if and by the time any of the party's products based on the HT-Core is openly promoted or sold. A royalty-free HyperTransport technology license can be acquired by simply becoming a member of the HyperTransport Technology Consortium. Complete information about HyperTransport Consortium membership classes, benefits, fees and application guidelines can be found here.

Last modified: 02.05.2011

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Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: coeht{at}ziti.uni-heidelberg.de

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