HT-Core Xilinx Virtex 4 FX port

The Computer Architecture Group (CAG) is proud to announce the availability of the HT-Core for Xilinx Virtex-4 devices. The core implements a complete 16-bit HyperTransport cave device and can be mapped onto an Xilinx Virtex-4 FPGA. The HT-Core is released under an open-source license.

The Xilinx version of the core uses clocking, input/output and FIFO ressources of the Xilinx architecture. Specifically this involved effective use of OSERDES/ISERDES, BITSLIP, IDELAY, DCM_ADVANCE, BlockRAM, SRL16 and FIFO primitives. The rest of the Core is written in architecture agnostic HDL code and cleanly implemented using the ISE Foundation 9.2 software from Xilinx.

The resulting FPGA image has successfully been loaded onto Virtex-4 FX60 and FX100 devices on the HTX-Board. Both an Iwill DK8-HTX based system and an HP DL145G3 machine have been used to test the core.

The current Xilinx implementation supports up to 16-bit wide links with speeds of HT200 and HT400. This provides a bi-directional bandwidth of 3.2 GB/s.

In system uni-directional effective data bandwidths of more than 1.4 GB/s and a host-to-device read latency of 180 ns were measured (HP DL145G3).

The current release of the HT-Core includes the version for Xilinx FPGAs as well as an example design. It is available for download from the CoEHT download page.

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Last modified: 02.05.2011