University of Heidelberg Institute of Computer Engineering




HT-Core Xilinx Virtex 4 FX port

The Computer Architecture Group (CAG) is proud to announce the availability of the HT-Core for Xilinx Virtex-4 devices. The core implements a complete 16-bit HyperTransport cave device and can be mapped onto an Xilinx Virtex-4 FPGA. The HT-Core is released under an open-source license.

The Xilinx version of the core uses clocking, input/output and FIFO ressources of the Xilinx architecture. Specifically this involved effective use of OSERDES/ISERDES, BITSLIP, IDELAY, DCM_ADVANCE, BlockRAM, SRL16 and FIFO primitives. The rest of the Core is written in architecture agnostic HDL code and cleanly implemented using the ISE Foundation 9.2 software from Xilinx.

The resulting FPGA image has successfully been loaded onto Virtex-4 FX60 and FX100 devices on the HTX-Board. Both an Iwill DK8-HTX based system and an HP DL145G3 machine have been used to test the core.

The current Xilinx implementation supports up to 16-bit wide links with speeds of HT200 and HT400. This provides a bi-directional bandwidth of 3.2 GB/s.

In system uni-directional effective data bandwidths of more than 1.4 GB/s and a host-to-device read latency of 180 ns were measured (HP DL145G3).

The current release of the HT-Core includes the version for Xilinx FPGAs as well as an example design. It is available for download from the CoEHT download page.

Description

The HT-Core provides an efficient way to build user specific devices by mapping the core and device modules to a programmable logic device connected to the HyperTransport Link. It provides a comfortable and efficient way to evaluate user specific devices connected to the HyperTransport connector standardized under the name HTX-Connector.

The HT-Core is a non-coherent HyperTransport cave device. A cave is an endpoint device in a HyperTransport chain. The core is a low latency device with a queue based application interface. Three queues are provided in each direction:
  • posted queue
  • non-posted queue
  • response queue
The HT200 interface delivers 1.6 GByte/s of bidirectional bandwidth and a very low latency of 300 ns (PIO Read).
The HT400 interface delivers 3.2 GByte/s of bidirectional bandwidth and an unrivaled low latency of 180 ns (PIO read).

Scope of delivery

  • Verilog source code for mapping to Xilinx Virtex4 FX series FPGAs. Verified on the HTX-Board Computing environment: Iwill DK8-HTX mainboard with LINUX-BIOS and HTX board.
    A constraint file in Xilinx .ucf file format describing the pinout is included.

Board Image

License

The HT-Core is available under an open source license to any interested party. The acquiring party will be obligated to secure a HyperTransport technology license if and by the time any of the party's products based on the HT-Core is openly promoted or sold. A royalty-free HyperTransport technology license can be acquired by simply becoming a member of the HyperTransport Technology Consortium. Complete information about HyperTransport Consortium membership classes, benefits, fees and application guidelines can be found here.

Last modified: 02.05.2011

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Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: coeht{at}ziti.uni-heidelberg.de

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