University of Heidelberg Institute of Computer Engineering


 


HTCE Logo Second Symposium of the HyperTransport™ Center of Excellence

Mannheim, February 11-12th, 2009
 
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General Information

The goal of the HyperTransport™ Center of Excellence (HTCE) Symposium is to present research results and new developments in the area of HyperTransport. Especially the research at the Computer Architecture Group of the University of Heidelberg in close cooperation with AMD will be reported. The mission is to support and promote the use and application of the HyperTransport interconnect technology to research and industry. The Symposium will bring together experts in the field of HyperTransport, high performance processors and FPGA co-processing.
As an accompanying event to the 2nd Symposium the First International Workshop on HyperTransport Research and Applications (WHTRA) takes place, serving as a forum for peer reviewed papers in the area of HyperTransport.


Program

The 2nd Symposium starts on Wednesday (Feb. 11th) with the registration at 08:00 (p.m.) and in the evening of this day the social event of the Symposium takes place. The second day of the event (Thursday) is dedicated to the accompanying workshop (First International Workshop on HyperTransport Research and Applications).

The first day of the Symposium consists of several invited talks as key notes, followed by technical sessions. We are proud to announce the following highly renowned speakers from both industry and academia.
The key notes include updates about the most recent developments in the area of HyperTransport, an outlook on upcoming developments and technologies and the impact of HyperTransport on not only PGAS (Partitioned Global Address Space) but other cost and power savings in large blade systems as a consequence. As the developments of the HTCE are mostly available as Open Source we invited the long-term Open Source endorser Monty Widenius, who is one of the initial developers of the popular MySQL database. He will present how business models can be developed based on Open Source.
The remaining program will consist of technical sessions, in which in-depth talks on current developments are presented. The first day of the Symposium ends with a social event, giving the participants the opportunity to meet and establish direct contacts.

 
Key Notes
Welcome Address and Update on HTCE's work Prof. Dr. Ulrich Brüning
University of Heidelberg & HyperTransport Center of Excellence
HyperTransport Technology in 2009 and beyond Mike Uhler,
Vice President, Accelerated Computing, AMD
HyperTransport - Extending Technology Leadership Mario Cavalli,
General Manager, HyperTransport Technology Consortium
Open Source Business Models Monty Widenius,
MySQL Founder
System Impact of Integrated Interconnects Prof. Sudhakar Yalamanchili,
School of Electrical and Computer Engineering,
Georgia Institute of Technology

Technical Talks
Building blocks for custom HyperTransport Solutions Dr. Holger Fröning
University of Heidelberg & HyperTransport Center of Excellence
Maintaining Cache Coherence with AMD Opterons using FPGAs Parag Beeraka
AMD
Scalable OpenMP Programming Dieter an Mey & Christian Terboven
RWTH Aachen
Leveraging HyperTransport for a custom high-performance cluster network Mondrian Nüssle
University of Heidelberg & HyperTransport Center of Excellence
Procyon - The ultra-high performance simulation and control platform with HyperTransport Satoshi Furukawa
A & D Technology




On the second day of the Symposium the First International Workshop on HyperTransport Research and Applications (WHTRA) takes place, in which peer reviewed papers are presented. The key note of the workshop will be held by Prof. José Duato from the Universidad Politècnica de Valencia (Spain), who will talk about role of HyperTransport in future system architectures and how it can be used to overcome the current power and memory walls: Beyond the power and memory walls: The role of HyperTransport in future system architectures

Intended Audience

A broad range of applications can benefit from the HyperTransport technology with its lean and efficient protocol. It's use is not limited to AMD products, you can also find HyperTransport in NVidia products or IBM's PowerPC architecture.
The most recent development is the HyperTransport 3.1 (HT3) and HTX3 specification. In the first step this emerging technology which will be used mainly by AMD processors. HT3 units can either be located on the mainboard, in the CPU socket or on an HTX3 add-in card. In all cases HT units are directly connected to the CPU(s) without any intermediate bridges or any kind of protocol conversion. Custom HT3 units will emerge as soon as HT3 CPUs are available. 
The high performance of HT3 in terms of extremely high bandwidth of up to 51.2 GByte/s (maximum theoretical bandwidth for a 32 bit wide HT 3.1 link) and low latency due to the direct connection makes it highly suitable for high performance applications. Additionally, the direct connection allows to participate in the cache coherency protocol of the CPUs. Typical applications are accelerated computing, fine grain communication and distributed shared memory.
If you are interested in the HyperTransport technology or want to learn more about the performance and scalability of AMD processors in combination with reprogrammable co-processors then this Symposium will provide you with the latest information on HyperTransport and show you how to implement your own accelerator tailored to your application.
You will meet leading industry executives from AMD and other companies that have invested in HT technology as well as academic researchers working in the field of high performance computing architectures.

Gallery

You can view the pictures from the event here:

Contact

For issues regarding the organization of the Symposium, please contact Holger Fröning (holger.froening {at} ziti.uni-heidelberg.de).

For further information or general inquiries related to the HyperTransport Center of Excellence please send an email to htce {at} ziti.uni-heidelberg.de.

Last modified:02.05.2011

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Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: coeht{at}ziti.uni-heidelberg.de

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