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Description
The HTX-Board provides a comfortable and efficient way to evaluate user specific devices connected to the Hypertransport connector standardized under the name HTX-Connector™. The HTX-Board with the 16bit wide bidirectional HTX Interface can be plugged to any AMD Opteron™ processor node with HTX. The HT400 interface will deliver 3.2GByte/s bandwidth and a very low latency. Various additional standard interfaces are available or can be added to the board by two mezzanine connectors.The HTX-Board combines the following items: a Hypertransport HTX connector, one of the most complex Xilinx FPGAs - a Virtex-4 FX100 as the programmable core logic, several high speed serial links (MGT -> SFP, MGT -> SATA), a 32bit wide DRAM, a user FLASH memory, a Gigabit-Ethernet PHY with RJ45-Connector and the programming infrastructure.
A Xilinx platform PROM memory is used for FPGA configuration after power-on. A JTAG and a USB1.1 interface is provided for programming the FPGA and the platform PROM. The USB interface can also be used for FPGA to PC communication.
Technical Specification
- HTX Connector with 16bit wide bidirectional interface
- FPGA Virtex-4 FX100 (FX60 on request)
- Speed grade -11, (-12 on request)
- 2 PowerPC cores For more details please refer to the Xilinx Virtex4 FX60 user manual.
- 256MB of DDR2 DRAM, 32bit interface to FPGA (others on request)
- 512 Mbit of user FLASH, 16bit interface to FPGA
- 125MHz low jitter clock oscillator
- Complete power supply over HTX connector, no external power supply required
- Power consumption of 6 to 24W (depending on configuration)
The HTX-Board is a development of the University of Mannheim, Computer Architecture Group. It has been partly funded by the European Union in the context of the FutureDAQ Project under contract number RII3-CT-2004-506078.
Documentation
- Flyer
with basic information (htx_board_data_sheet_u2.pdf)
Short datasheet (one side) with most important facts regarding the HTX-Board. - Extended
information brochure (htx_board_extended_data_sheet_u3-htc.pdf)
(also available on http://www.hypertransport.org)
Extended datasheet with more advanced informations - ISC2006
booth slides (isc2006_HTC_website.pdf) (also available on
http://www.hypertransport.org)
Presentation slides shown at the International Supercomputer Conference in Dresden, Germany (ISC 2006). This presentation was shown both on the AMD booth and on the HP booth. Contains an overview of important HTX-Board features and all other building blocks, like the HT-Core running the HT-protocol, the HTX-Extenders for measurements of the HTX interface, the Mezzanine cards for the HTX-Board, programming of the FPGA...
Downloads
Reference Design of the HyperTransport Consortium
The HTX-Board is also presented on the HTC's product site: http://www.hypertransport.org/default.cfm?page=ProductsViewProduct&ProductID=75
Images
Assembled Prototype HTX-Board with Virtex4 FX60 (242 KB)
Blockdiagram of the HTX-Board (320 KB)
Contact
Holger Fröning, email: holger.froening {at} ziti.uni-heidelberg.deLast modified:02.05.2011
Lectures
SS 12
Digital Semi Custom Design Flow
Functional Verification
High Performance Interconnects
Entrepreneurship
Seminar Hardwareentwurf u. Optik
WS 11/12Functional Verification
High Performance Interconnects
Entrepreneurship
Seminar Hardwareentwurf u. Optik
Contact
Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: ulrich.bruening {at} ziti.uni-heidelberg.de
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: ulrich.bruening {at} ziti.uni-heidelberg.de
Delivery Address
Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68159 Mannheim
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68159 Mannheim
HT Center of Excellence
