Ruprecht-Karls-Universität Heidelberg

Cadence Academic Network

The Cadence Academic Network was launched in 2007. The aim is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected universities, research institutes, industry advisors, and Cadence facilitates the sharing of technology expertise in the areas of verification, design, and implementation of microelectronic systems.

The Computer Architecture Group of the Heidelberg University is a member of this network as the Lead University for Functional Verification.

The Cadence Academic Network also distributes its information via the LinkedIn network. The groups are moderated by the lead institutions, which ensures a constant flow of reviewed information relevant to academia. Visit the Cadence Academic Network LinkedIn Group and its subgroup for Advanced Verification Methodology to find links to interesting webinars, videos, articles, technical demos, upcoming events, and a lot more.


The Computer Architecture Group leverages Cadence tools to provide students with hands-on-experience of state-of-the-art EDA tools in our courses on hardware design, verification, and implementation.

Currently, we offer the classes "Digital Hardware Design", "Functional Verification" and "Digital Semi Custom Design Flow" to teach students the entire digital design flow from RTL to GDS2 as well as cutting-edge verification methodologies.


The research activities of our group mainly focus on the development of high performance interconnects and processor technologies. A selection of research projects can be found on our recent research projects overview.

One of our research areas focuses on the design of VLSI components. To ensure an efficient workflow, we use Cadence's PCellDesigner. The tool allows the geometrical specification of parameterizable cells. This can also be applied to all commonly used design elements, which eliminates the need to build them manually each time. PCellDesigner not only saves a lot of time, but also provides more consistent and less error-prone results than the traditional way.

As complex digital designs require extensive verification, we are always employing state-of-the-art verification technologies. As Lead University for Functional Verification within the Cadence Academic Network, we are looking forward to spread verification knowledge throughout the network.


Years before the Cadence Academic Network was formed, we already saw the need to improve education in the field of semi-custom/full-custom ASIC design. In order to do so, we established the SEED project in 2002, which was a cooperation between Cadence and the Universities of Mannheim, Heidelberg, and Kaiserslautern.

When the Cadence Academic Network formed, it was a natural choice to host the first Cadence Academic Network (CAN) Day at our place in 2006. In the meantime, the CAN day has evolved to an academic track at the annual CDNLive Conference. Past research activities include the HyperTransport Center of Excellence, which was established together with AMD.

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