Ruprecht-Karls-Universität Heidelberg

1st European Summer School on
Functional Verification

Summer School Functional Verification 2015The functional complexity of SoCs grows with each new chip generation. Meanwhile, the development time for an SoC doesn't increase due to time to market constraints. Therefore, strong functional verification methodologies are needed to ensure the functional correctness of a design before tape-out. These methodologies have to address problems like stimulus generation for the SoC, and checking of the designs behavior. Furthermore, sign off criteria need to be provided to be able to track the verification process.

The Summer School on Functional Verification brings together undergraduate and graduate students with functional verification experts to educate them with state of the art functional verification techniques. It is organized by the Computer Architecture Group at the Institute of Computer Engineering of Heidelberg University and supported by the Cadence Academic Network. It will take place in Mannheim, Germany, from September 7th to September 11th, 2015.


The following topics will be covered:

  • The Verification Cycle
  • Verification Planning
  • Stimulus Generation
  • Checking of the Design under Verification
  • Functional Coverage Analysis
  • Regression Management
  • UVM-e
  • SystemVerilog Assertions
  • Formal Verification

Each module consists of lectures and related hands-on exercises.


  • Basic understanding of the hardware design process
  • Some programming skills with an OOP language, e.g. Java
  • Knowledge of a hardware description language (Verilog, VHDL) is beneficial


In order to register for the summer school fill in the registration form.

  • The registration deadline is July 15th, 2015
  • The registration fee is 200 Euro
  • The number of attendees is limited due to classes and labs capacity

The fee includes lunch, coffee breaks, a social event, course materials, and refreshments.

For further information feel free to contact us: scfv{at}

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