Ruprecht-Karls-Universität Heidelberg

Journal and Conference Papers


  • Bharti Wadhwa, Arnab Paul, Sarah Neuwirth, Feiyi Wang, Sarp Oral, Ali Butt, Jon Bernard, Kirk Cameron
    iez: Resource Contention Aware Load Balancing for Large-Scale Parallel File Systems
    33rd IEEE International Parallel and Distributed Processing Symposium (IPDPS 2019), May 20-24, 2019, Rio de Janeiro, Brazil.
  • Tobias Markus, Markus Mueller, Ulrich Bruening
    Schematic Generation Framework in a Mixed Signal Top Down Design Flow
    22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019), April 24-26, 2019, Cluj-Napoca, Romania.
  • Felix Kaiser, Stefan Kosnac and Ulrich Bruening
    Implementation of a RISC-V-Conform Fused Multiply-Add Floating Point Unit
    Supercomputing Frontiers Europe 2019, March 11-14, 2019, Warsaw, Poland.


  • Stefan Kosnac and Ulrich Bruening
    Design Flow Automation for On-Chip Inductors
    Cadence User Conference 2018 (CDNLive EMEA 2018), Academic Track, May 7-9, 2018, Munich, Germany.


  • Sarah Neuwirth, Feiyi Wang, Sarp Oral, Ulrich Bruening
    Automatic and Transparent Resource Contention Mitigation for Improving Large-scale Parallel File System Performance
    23rd IEEE International Conference on Parallel and Distributed Systems (ICPADS 2017), Dec. 15-17, 2017, Shenzhen, China.


  • Sarah Neuwirth, Feiyi Wang, Sarp Oral, Sudharshan Vazhkudai, James Rogers, Ulrich Brüning
    Using Balanced Data Placement to Address I/O Contention in Production Environments
    28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2016), Oct. 26-28, 2016, Los Angeles, California, USA.
    - Best Paper Award -
  • Juri Schmidt, Holger Fröning, Ulrich Brüning
    Exploring Time and Energy for Complex Accesses to a Hybrid Memory Cube
    The international Symposium on Memory Systems (MEMSYS 2016) Oct. 3-6, 2016, Washington D.C, USA.


  • Sarah Neuwirth, Dirk Frey, Ulrich Bruening
    Communication Models for Distributed Intel Xeon Phi Coprocessors
    21st IEEE International Conference on Parallel and Distributed Systems (ICPADS 2015), Dec. 14-17, 2015, Melbourne, Australia.
  • Juri Schmidt, Ulrich Brüning
    openHMC - A Configurable Open-Source Hybrid Memory Cube Controller
    10th IEEE International Conference on ReConFigurable Computing and FPGAs, Dec. 7-9, 2015, Mayan Riviera, Mexico.
  • Ulrich Bruening, Mondrian Nuessle, Dirk Frey
    An Immersive Cooled Implementation of a DEEP Booster
    Intel European Exascale Labs Annual Report 2014, July 2015.
  • Sarah Neuwirth, Dirk Frey, Mondrian Nüssle, Ulrich Brüning
    Scalable Communication Architecture for Network-Attached Accelerators
    21st IEEE International Symposium on High Performance Computer Architecture (HPCA 2015), Feb. 7-11, 2015, Bay Area, California, USA. (acceptance rate: 21%, 51/231, ranking: core A*)


  • Sven Kapferer, Markus Müller, Ulrich Brüning
    Implementation of a Complex Network ASIC in an Academic Environment
    CDNLive EMEA 2014, Academic Track, May 19-21, 2014, Munich, Germany.
  • Sven Schatral, Frank Lemke and Ulrich Brüning
    Design of a deterministic link initialization mechanism for serial LVDS interconnects
    Journal of Instrumentation, doi:10.1088/1748-0221/9/03/C03022,
    VOL. 9, No. 03,  pages C03022, March 2014.


  • Mondrian Nüssle, Holger Fröning, Sven Kapferer, Ulrich Brüning
    Accelerate Communication, not Computation!
    High Performance Computing Using FPGAs, p. 507-542, Vanderbauwhede, Wim; Benkrid, Khaled (Eds.), Springer, 2013.


  • B.Mohr, N.Zimmermann, B.T.Thiel, J.H.Mueller, Y.Wang, Y.Zang, F. Lemke, R.Leys, S.Schenk, U. Brüning, R.Negra, S.Heinen
    An RFDAC Based Reconfigurable Multistandard Transmitter in 65nm CMOS
    IEEE 2012 RFIC Symposium, June 17–19, 2012, Montreal, Canada.
  • Frank Lemke, Ulrich Brüning
    Design Concepts for a Hierarchical Synchronized Data Acquisition Network for CBM
    IEEE 18th Real-Time Conference 2012 (RT12), June 11–15, 2012, Berkeley, CA, USA.


  • Bastian Mohr, Niklas Zimmermann, Yifan Wang, Björn Thorsten Thiel, Renato Negra, Stefan Heinen;
    Frank Lemke, Sven Schenk, Richard Leys, Ulrich Brüning
    Implementation of an RF-DAC based Multistandard Transmitter System
    CDNLIVE! 2011, Academic Track, May 3–5th, 2011, Munich, Germany.


  • Heiner Litz, Maximilian Thürmer, Ulrich Brüning
    A Cluster Architecture Utilizing the Processor Host Interface as a Network Interconnect
    CLUSTER 2010, September 20–24, 2010, Heraklion, Greece. [pdf]
  • Frank Lemke, David Slogsnat, Niels Burkhardt, Ulrich Bruening
    A Unified DAQ Interconnection Network with Precise Time Synchronization
    IEEE Transactions on Nuclear Science (TNS), Journal Paper, VOL. 57, No. 2, APRIL 2010.


  • Jose Duato, Federico Silla, Brian Holden, Paul Miranda, Jeff Underhill, Mario Cavalli, Sudha Yalamanchili, Ulrich Brüning and Holger Fröning
    Scalable Computing - Why and How
    HyperTransport Consortium White Papers, 2009.



  • David Slogsnat, Alexander Giese and Ulrich Bruening
    Leveraging HyperTransport on Xilinx FPGAs
    Xilinx Xcell Journal, Issue 61, July 2007.


  • Holger Fröning, Mondrian Nüssle, David Slogsnat, Heiner Litz, Ulrich Brüning
    The HTX-Board: A Rapid Prototyping Station
    3rd annual FPGAworld Conference, Nov. 16, 2006, Stockholm, Sweden. [pdf]



  • Ulrich Bruening, Wolfgang Giloi
    Future Building Blocks for Parallel Architectures
    Proceedings of the 2004 International Conference on Parallel Processing (ICPP.04), Montreal, CA, 2004. [pdf]


  • Ulrich Bruening, Ulrich Krackhardt
    Systeme fuer eine hocheffiziente elektrische und optische Kurzstreckenuebertragung im SAN-Bereich
    it - Information Technology 02/2003, Oldenbourg Verlag, pp. 65–71, April 2003.
  • David Slogsnat, Patrick R. Haspel, Holger Fröning and Ulrich Bruening
    The ATOLL System Area Network (SAN)
    IEEE Task Force Cluster Computing Newletter, September 2003.
  • David Slogsnat, Patrick. R. Schulz, Ulrich Brüning
    Lessons Learned from Using Superlog, SystemVerilog's Predecessor
    Forum on Specification & Design Languages (FDL), September 23–26 2003, Frankfurt, Germany. [pdf]



  • Lars Rzymianowicz, Mathias Waack, Ulrich Brüning, Markus Fischer, Jörg Kluge and Patrick Schulz.
    Clustering SMP Nodes with the ATOLL Network: A Look into the Future of System Area Networks
    HPCN 2000, April 1–5 2000, Amsterdam, NL. [pdf]
  • Markus Fischer, Ulrich Brüning, Jörg Kluge, Lars Rzymianowicz, Patrick Schulz and Mathias Waack.
    Impact of Configurable Network Features in ATOLL
    APSCC 2000, May 14–17, 2000, Beijing, P.R. China. [pdf]
  • Jörg Kluge, Ulrich Brüning, Markus Fischer, Lars Rzymianowicz, Patrick Schulz and Mathias Waack.
    ATOLL - A Next Generation System Area Network
    HPC Asia 2000, The Fourth International Conference/Exhibition on High Performance Computing in Asia-Pacific Region, May 14–17 2000, Beijing, P.R. China. [pdf]
  • Markus Fischer, Ulrich Brüning, Jörg Kluge, Lars Rzymianowicz, Patrick Schulz and Mathias Waack.
    ATOLL, a new switched, high speed Interconnect in Comparison to Myrinet and SCI
    IPDPS 2000, PC NOW Workshop, May 1–5 2000, Cancun Mexico. [pdf]


  • Jörg Kluge, Ulrich Brüning, Markus Fischer, Lars Rzymianowicz, Patrick Schulz and Mathias Waack.
    The ATOLL approach for a fast and reliable System Area Network
    Third Intl. Workshop on Advanced Parallel Processing Technologies (APPT'99) conference, October 19–21 1999, in Changsha, P.R. China. [pdf]
  • Ulrich Brüning, Jörg Kluge, Lars Rzymianowicz, and Mathias Waack.
    FSMDesigner: Combining a Powerful Graphical FSM Editor and Efficient HDL Code Generation with Synthesis in Mind
    8th International HDL Conference and Exhibition HDLCON'99, April 6–9, Santa Clara, CA..

  • Lars Rzymianowicz, Ulrich Brüning, Jörg Kluge, Patrick Schulz and Mathias Waack.
    ATOLL: A Network on a Chip
    Cluster Computing Technical Session (CC-TEA) of the PDPTA'99 conference, June 28–July 1 1999, in Las Vegas, NV. [pdf]
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