Ruprecht-Karls-Universität Heidelberg


FSMDesigner2

Note

This page desribes the FSMDesigner2 Software which is no longer supported by us. You may download the software and use it AS IS, but do not expect any support from us. We are working on a brand new, modern version of the software incorporating all the features of FSMDesigner2 and adding new ones.

Description

FSMDesigner is a Java-based Finite State Machine (FSM) editor, which allows the hardware designer to specify complex control circuits in an easy and comfortable way. The graphical FSM is converted into a proprietary state/flow-table format called fsm2. It can be translated into efficient and synthesizable Verilog HDL code by a compiler called fsm2v designed at our chair. FSMDesigner is based on the Simple-Moore FSM model, which completely eliminates the output function by using parts of the state vector as outputs.

Here is a short list of its functions:

  • several FSMs can be specified in one module
  • single states or transitions and even whole parts of the FSM can be copied
  • state images (state labels) support a clear design style
  • default transitions can be expanded to verify the terms covered by them
  • a checker can be applied to automatically detect inconsistencies and uncovered input conditions
  • the whole module can be simulated with a step-by-step method highlighting the actual state and transition
  • interfaces are implemented to use the FSMDesigner together with other tools during trace-based (VCD) simulation
  • annotations for documentation purposes can be inserted
  • variability of the look-and-feel through a user-configurable init-file

Screenshots

Picture of a module 

Figure 1: Showing a module consisting of 3 FSMs, a dialog for editing a transition in the upper right corner

 Picture of a simple 2bit counter FSM

Figure 2: Showing a simple 2bit counter FSM, the step-by-step simulation dialog in the lower left corner and highlighted current state and next transitionx

Evaluation

We presented the FSMDesigner on the HDLCON '99 conference. We compared our coding style to other common implementation techniques and evaluted them with respect to synthesis results.

  • Here is the Abstract:
    Today, complex control hardware is mostly implemented by using Finite State Machines (FSM). An efficient synthesizable HDL (Hardware Description Language) code is the key element for meeting timing and area constraints of high-speed hardware designs containing FSMs. On one hand, several tools for graphical specification and simulation of FSMs have been developed. On the other hand, the optimization of HDL code has been left to synthesis tools.
    Our tool FSMDesigner combines both features, thus enabling the generation of efficient synthesizable HDL code directly from a high-level graphical FSM representation. We achieve this by selecting the Simple-Moore FSM model and the application of a logic minimization step. The output only contains minimized sum-of-products logic, an ideal base for following synthesis steps. Since it is difficult to compare the functionality of different FSM editors, this paper focuses on the comparison of FSM implementation styles, HDL code generation techniques and their efficiency. We evaluate the synthesis results for a given FSM and present the advantages of our design style.

Download

For Solaris 2.5.1 or higher (589KB)
For Linux (395KB)
For Windows 95, 98, NT4.0 (817KB)

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