Ruprecht-Karls-Universität Heidelberg


Recent Research Projects

  • Cadence Academic Network
    The Cadence Academic Network was launched in 2007. The aim is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected universities, research institutes, industry advisors, and Cadence facilitates the sharing of technology expertise in the areas of verification, design, and implementation of microelectronic systems.The Heidelberg University, specifically the Computer Architecture Group, is a member of this network as the Lead Institution for Advanced Verification Methodology.
  • DEEP - Extreme Scale Technologies (DEEP-EST)
    The Modular Supercomputer Architecture (MSA) developed in the DEEP-EST research project is a blueprint for heterogeneous HPC systems supporting the divergent computation and data processing requirements of high performance compute and data analytics with highest efficiency and scalability. The MSA is based on the Cluster-Booster architecture developed in the previous DEEP and DEEP-ER projects. The MSA interconnection network is based on EXTOLL, encapsulated in a dense form factor box called FabriCube. In cooperation with EXTOLL, the Computer Architecture Group is responsible for the design and implementation of two key components, which serve two different use cases: (1) Network Attached Memory (NAM) provides network-speed access to up to 64TB non-volatile storage. It can serve as an intermediate storage target to, for example, hold machine learning training data. Its functionality is complemented by application specific processing elements to execute small compute kernels. (2) The Global Collective Engine (GCE) is equipped with two DDR4 memory DIMMs. These function as a buffer for data elements required to process global collective operations "in the network". Collective operations are among the most commonly used communication patterns in HPC applications. Hence, accelerating these operations will likely improve application runtimes and system efficiency. The DEEP-EST project has officially started in July 2017 and is expected to end in June 2020.

  • Human Brain Project (HBP)
    The Human Brain Project (HBP) aims to understand how the inconceivably efficient system of the human brain works. For this purpose, it uses the method of synthesis biology. This means that it tries to understand the biological system from the bottom-up direction instead of using the conventional analytic top-down methodology. The BrainScaleS system at the Kirchhof-Institute for Physics (KIP) in Heidelberg is part of the HBP and pursues this goal by developing a neuromorphic analog hardware system in combination with a conventional computing cluster. Up to now, the communication FPGAs have been connected through an Ethernet network using USB 3.0 cables. In collaboration with the Computer Architecture Group, the KIP develops a new network interface for the FPGAs controlling the data communication between the neuromorphic hardware chips and the conventional digital system. This new network interface will utilize the benefits of the EXTOLL network technology, a high-performance interconnection network, which is optimized for low latency and high message rates.
  • RISC-V Processor Design
    The goal of this research project is to design a 64bit 6-stage pipelined processor based on the RISC-V instruction set architecture (ISA). The design will be implemented using SystemVerilog and will try to make the processor as fast as possible and at the same time highly energy-efficient. The design will be used to study the architectural challenges of adding new instructions and interfaces for low-latency accelerators and communication units. First results include a fully verified IEEE compliant floating-point multiply-add unit. The next extensions are planned to include a POSITs unit for high-precision floating-point calculations. The code is fully synthesizable with standard cell libraries. A design for the GlobalFoundries 22nm FDX process is in development. Special optimizations can be achieved by using bit cell kits for the memory structures.
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