Ruprecht-Karls-Universität Heidelberg

Research Associate / Ph.D. Candidate



Tobias Markus
Computer Architecture Group, Heidelberg University
Institute of Computer Engineering (ZITI)
Im Neuenheimer Feld 368 (5th floor)
69120 Heidelberg, Germany

Room: 503
E-Mail: tobias.markus {at}
Tel: +49 (0)6221-54-16362

Teaching Experience:

  • SoSe18: Teaching Assistant, Digital Semi Custom Design Flow
  • WiSe17/18: Teaching Assistant, Einführung in die Technische Informatik
  • WiSe16/17: Teaching Assistant, Einführung in die Technische Informatik
  • Supervision of Master and Bachelor Theses


Conference Contributions and Paperwork

  • Tobias Markus, Markus Mueller, Ulrich Bruening
    Accurate System-level RNM modelling in Multi-gigabit-transceivers
    Design Automation Conference 2018 (DAC 2018), IP Track: New Challenges for IP and VIP to Support Emerging Application or Algorithm, June 24-28, 2018, San Francisco, CA, USA.
  • Tobias Markus, Markus Mueller, Ulrich Bruening
    A Generator Approach for Full Custom Parts in a Top Down Flow
    Design, Automation, Test in Europe Conference & Exhibition 2018 (DATE 2018), University Booth, March 19-23, 2018, Dresden, Germany.
  • Tobias Markus, Markus Mueller, Maximilian Thuermer, Stefan Kosnac, Mondrian Nuessle, Ulrich Bruening
    Performance Verification of an Digital PLL for use in Multi-Gigabit-Transceivers
    Design Automation Conference 2017 (DAC 2017), IP Track: Security and Reliability of IP Subsystems, June 18-22, 2017, Austin, TX, USA.
  • Tobias Markus, Niels Burkhardt, Ulrich Bruening
    RFG: A Language for Register File Generation
    Cadence User Conference 2016 (CDNLive EMEA 2016), Canvas Conversations, May 2-4, 2016, Munich, Germany.

Master Thesis

  • Tobias Markus
    High-Speed Clock Generation Architecture for a Multi-Rate SerDes in 28nm
    Master thesis
    University of Heidelberg, Nov. 2015.

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