Ruprecht-Karls-Universität Heidelberg

Design of a 6-Stage pipelined Processor Core based on the RISC-V Instruction Set Architecture

Bachelor Thesis by Thomas Buehler


Due to the increasing popularity of the newly developed, open RISC-V instruction set architecture, unprecedented possibilities for hardware design start to appear, that lead to increased developments in research. However, in the field of High-Performance Computing only a slim variety of processor cores are represented. This work revolves around the development of a 64-bit RISC-V-compliant processor core that should implement the base instruction set. It is designed upon the principle of pipelining and should, among other things, serve as a foundation for further research in High-Performance systems. Furthermore, the development of a fast jump resolve is discussed and several points, that are needed in order to result in an efficient hardware design are considered. Within the scope of this work the simulation of a small C-program was achieved. With the aim to be able to later run a Unix-like Operating System, the task of the Control- and Status register and the Exception Handler is presented


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