Ruprecht-Karls-Universität Heidelberg

Exploiting Instruction-Level Parallelism - Hardware Structures for a Superscalar Out-of-Order Processor

Bachelor Thesis by Amanda Matthes


Superscalar out-of-order execution has become the norm in modern processors. Yet there is little information in the literature about its implementation details. This thesis explores what new hardware structures superscalar out-of-order execution requires. It presents a design for a simple processor, implemented in SystemVerilog, that uses register renaming, reservation stations and a reorder buffer to dynamically schedule instructions.


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