Ruprecht-Karls-Universität Heidelberg

Development and Verification of a HyperTransport-Interface with Optimizations for FPGA Environments

Diploma Thesis by Alexander Giese


This diploma thesis presents the development of an HyperTransport core. HyperTransport is a packet-based interconnect technology for low-latency, high-bandwidth point-to-point connections. This work focuses on developing this core to be used on cards that can be plugged into HyperTransport slots. Nevertheless, the core may be used in any other Hypertransport environment as well. The work examines and describes the features of the HyperTransport protocol that have to implemented to get a fully-functional device implementing the fundamental HyperTransport functionality that is needed when being used in AMD Opteron-based systems. The whole development process including implementation and evaluation is covered in this thesis and a synthesizeable hardware description language (HDL) of the complete design is provided. The design is verified by simulation. Also, in-system verification is performed by mapping the core to an FPGA-based HyperTransport card.


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