Ruprecht-Karls-Universität Heidelberg


Improving and Extending a Crossbar Design for ASIC and FPGA Implementation

Diploma Thesis by Benjamin Geib

Abstract:

In this thesis, the EXTOLL Crossbar has been mapped to the Xilinx FPGA technology in order to be able to prototype the EXTOLL network chip. In addition to this mapping, a lot of changes have been made as well, in order to meet timing, adapt to new protocols and restrictions and achieve a higher fault tolerance. The second part of this document describes the exploration and implementation of a module for EXTOLL called the HAP, which in addition to the changes to the Crossbar, makes EXTOLL in all more tolerant against faults. The result is a fully synthesizeable Verilog HDL description of the HAP.

 

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