Ruprecht-Karls-Universität Heidelberg

Design and implementation of a high speed serializing multipurpose interconnect with improved testability as a key aspect

Diploma Thesis by Boris Strohmeier


As the demand for high-speed data transmission in cluster computing systems grows, the bandwidth and latency of the communication channel becomes critical. Furthermore, not only the bandwidth is a critical resource, the cost performance ratio is a key issue, too. This ratio can be decreased by massive integration of all relevant components in a highly integrated ASIC (Application Specific Integrated Circuit), which is the aim of the OASE chip. OASE is a transceiver for high speed optical transmission with up to 2.5GBit/s. Only a mixed signal design is suitable for this purpose. The work presented here deals with the design of the OASE chip. This includes the complete digital design, selected parts of the analog design, the specification of the interfaces from digital to analog and the I/O planning of the ASIC.


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