Ruprecht-Karls-Universität Heidelberg

FPGA-based Implementation of Alternative Memory Consistency Models

Diploma Thesis by Christian Leibig


In this diploma thesis, the capabilities of FPGA-based development are detailed by showing the possibility to test new consistency concepts directly in hardware. First, a general introduction to coherent HyperTransport is given and a cache coherent HyperTransport memory controller for DDR2 is developed and detailed. The underlying system’s coherency behavior is then modified with the goal of testing the concept of Asymmetric Probing directly in-system. The thesis further provides an introduction to Transactional Memories, a novel and largely untested memory consistency scheme aiming to replace locking, which can benefit greatly from explicit hardware support. The possible benefits and drawbacks of Transactional Memories are detailed and two implementations, one noncoherent and the other coherent, are developed with the goal of realizing a Transactional Memory engine on an FPGA development card.



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