Ruprecht-Karls-Universität Heidelberg

System Design of an HT3 Verification Platform based on a high-performance FPGA

Diploma Thesis by Elmar Greulich


This diploma thesis describes the development of a HyperTransport (HT) Generation 3 (Gen3) verification platform based on a single high-performance FPGA. The platform is realized on a printed circuit board (PCB) and provides the opportunity to develop and verify devices as well as co-processors for the high data rate, low-latency HT Generation 3 technology, based on common HT systems. The technology is a high bandwidth, low latency system bus for connecting CPUs and devices on a point-to-point basis for system applications and scalable multiprocessing systems. The technology satisfies the requirements of high data throughput on modern interconnect solutions by simultaneous avoidance of protocol latency. The thesis gives a detailed view on the implementation and verification of this high-density interconnect PCB project, featuring a modern FPGA 40nm technology device. It presents the techniques and methods for a successful accomplishment of the high frequency HT Gen3 challenges as well as for the effective integration of a future FPGA device. This includes the presentation of design space decisions, signal integrity challenges, and simulation methodologies. Simulations were part of the FPGA characterization and PCB design process for verifying the HT Gen 3 design platform on a single FPGA.



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