Ruprecht-Karls-Universität Heidelberg


High Level Executable Specification Development of a high performance SAN chip

Diploma Thesis by Ingo Feldner

Abstract:

The challenges imposed by today’s multi-million gate chips have evoked fundamental changes in the traditional design and verification methodologies. Higher integration densities have lead to the possibility of integrating a complete system into a single chip. The high complexity of these designs demands for a fast implementation and exploration of design alternatives in order to avoid costly design iterations at a late stage in the design cycle. The introduction of System Level Design languages were clearly aimed at reaching this goal.
An integral part of System Level Design is Hardware/Software Co-design which denotes the parallel development of Hardeware and Software in order to speed up the overall design cycle.

This work describes the development of an executable specification of the ATOLL network interface in SystemC for the purpose of Hardware/Software Co-Design. The software environment developed in this way is then reused for the next generation ATOLL device - ExTOLL.
The ExTOLL architecture will contain a RMA engine and an embedded processor core. When integrating an embedded processor core on a network interface various problems like access to main memory, access to the network or program execution need to be considered. The design space exploration provides some suggestions on solving theses problems. Finally, the SystemC code of the core is integrated into the simulation environment and supplied with an instruction and data cache in order to simulate the memory access.

 

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