Ruprecht-Karls-Universität Heidelberg

Design, Implementation and Verification of a High Performance NAND Flash Based Storage System with HyperTransport Interface

Diploma Thesis by Jochen Kinzel


This diploma thesis focuses on the development and verification of a superscalar, high performance controlling hardware for Flash memory. It is part of a Flash memory based mass storage device, that is being developed by the Computer Architecture Group at the University of Heidelberg. The presented controlling hardware is able to manage up to 96 independent Flash memory units individually and in parallel. It is built-up from a hierarchical structure of 24 independent Flash microcontrollers (FMC), a single master controller and a high performance internal interconnection network. Each of the Flash microcontrollers supervises up to four Flash memory units. This arrangement is optimized for high throughput and low latency. An advanced instruction format is used, that allows for up to 1023 outstanding operations being issued to the master controller. An adequate system interconnection is established by providing an interface that is compatible with a slightly improved version of the HyperTransport protocol. Additionally, the developed verification environment is able to prove the controller's correct functionality. It is created by using the SystemVerilog language and the Open Verification Methodology (OVM) library. Furthermore, the controller has already been tested successfully in a real hardware implementation on a FPGA.

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