Ruprecht-Karls-Universität Heidelberg

Definition and Implementation of a Hardware Abstraction Layer (HAL) for an ASIC-Prototyping Station using a 64Bit/66MHz PCI interfaced FPGA

Diploma Thesis by Matthias Scheerer


ASIC development often lacks in-system-verification possibilities as long as no chip is produced. Much effort is spent for implementation of testbenches to replicate target environment behavior causing time-consuming simulation runs. But even highest effort in testing often can-t cover every situation the final ASIC will be exposed to. The outlined problem shows the need for a real-system environment where the design can be plugged in, tested and verified under mreal-system conditions. Stateof- the-art FPGA technology today enables such environments at affordable costs. Even if FPGAs are very limited in complexity, speed and functionality it is usually possible to build a rsneak previewc of the ASIC or parts of it. This thesis focuses on the definition and implementation of a hardware abstraction layer (HAL) which on the one hand provides ASIC engineers with easy-to-use interfaces to connect their designs to and on the other hand grants access to a 64 Bit / 66 MHz PCI bus to guarantee high bandwidth control and test possibilities. Important issues of coding and synthesis for high-speed FPGA designs are discussed as well as development of generic hardware interfaces. Additionally, a small PCI application programming interface (API) is implemented to cover software aspects of the PCI bus.


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