Ruprecht-Karls-Universität Heidelberg

Quality Analysis of back-end tools in a cell-based design flow of a high-performance multi-million gate ASIC

Diploma Thesis by Matthias Harter


The present work deals with the methodology of todays Application-Specific Integrated Circuit (ASIC) construction process, their design, practical implementation and theoretical cornerstones. It analyzes the crucial points and challenges in the design of cell-based ASICs, identifies the key elements and procedures and differentiates between important principles and minor matters. It prepares the physical implementation design flow, elaborates solutions to practical obstacles and shortcomings and provides the knowledge and experience an engineer must have to bring an up-to-date high-performance, multi-million gate System on a Chip (SoC) from RTL to silicon.


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