Ruprecht-Karls-Universität Heidelberg

Design for Test (DFT) and Testability of a Multi-Million Gate ASIC

Diploma Thesis by Patrick Schulz


To develop an ASIC beginning from the first concept idea over the Register Transfer Level (RTL) design, simulation, synthesis, test insertion, floorplan and place & route to the metal and polysilicon layers on the silicon wafer is a real challenge. The ATOLL System Area Network Chip developed by the Department of Computer Architecture at the University of Mannheim, Germany, guided me through the complete full-custom cell based ASIC design flow and I enjoyed participating in this project. The scope of this work covers the whole topic of test insertion, that is implementation of test architectures, integration of test structures and designing the test flow of the ATOLL Chip. Its was a challenge full of interesting discoveries to accompany a project of this enormous size and importance. My work begins with section 2: "Survey of Test Aspects" covering theoretical and commercial aspects of test and design-for-test (DFT). In section 3: "Test Principles" of this work, the principles how testability is provided and valued is explained. Fault models and their VLSI counterparts are also discussed, while section 4: "DFT Strategies" describes how these test principles are applied to a specific design. Finally in section 5: "Design Test Flow" is stated how this is done with the help of Electronic Design Automation (EDA) tools. With section 6: "Conclusion" I finish this work with a summary of the results and give a small "DFT" outlook in the near future..


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