Ruprecht-Karls-Universität Heidelberg

Design Space Analysis and Implementation of a Cache Coherent Device for HyperTransport

Diploma Thesis by Sven Kapferer


In this diploma thesis a coherent HyperTransport core is developed. The cHT protocol is a superset of the non-coherent protocol and is intended for the connection of CPUs, memory controllers and other devices in a cache-coherent fashion. The thesis provides background information about cache fundamentals and gives an introduction to the coherent HyperTransport protocol. In the following, design choices are introduced and several approaches are discussed. Additionally, the thesis presents the RTL implementation and the verification methodology that was used to get an operating core. The result is a synthesizable Verilog model of a coherent core together with a small cache that was both simulated and implemented in an FPGA and can be used in an AMD Opteron system.


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