Ruprecht-Karls-Universität Heidelberg

Architecture Analysis of Multi-Gigabit-Transceivers for Low Latency Communication

Diploma Thesis by Sven Schenk


High speed serial transceivers are commonly used in today's high performance computing systems. Despite providing excellent bandwidth per link, they perform poorly in terms of latency. The goal of this thesis is to develop operation principles, which enable high speed serial communication with low latency. An FPGA based design has been developed, which provides 44% less latency than with a traditional approach. Additionally, the transceivers of different FPGAs that are currently available on the market were evaluated based upon the technical specifications provided by their manufacturers. Their capabilities, in terms of communication latency, were examined in order to give an overview which helps to choose devices for future applications. Utilizing the designs presented in this thesis, the performance in a real-world environment was measured to verify the theoretical values of the evaluation. While low latencies are required by projects like the EXTOLL communication network, other projects, like the CBM project, require a deterministic latency. Designs fulfilling this requirement have also been developed. The development and the concepts of these designs are covered in this work, as well as the evaluation of the designs on the actual devices.


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