Ruprecht-Karls-Universität Heidelberg

Design, Implementation and Verification of a PCI Express to HyperTransport Protocol Bridge

Diploma Thesis by Timo Reubold


In this diploma thesis, a dependable, high bandwidth and low latency bridging mechanism between the PCI Express and HyperTransport data transfer protocols is developed. The goal was to supply Systems-on-a-Chip, relying on HyperTransport compatible integrated networks, with transparent and highly versatile PCI Express host-system connectivity. This work provides a brief introduction to PCI Express, HyperTransport and a derived on-chip interconnect, followed by a detailed transaction layer oriented review of both protocols. Conversion feasibility is analyzed and methods and solutions elaborated to carry out transaction-based protocol translation. These concepts are realized in synthesizable Verilog HDL code afterwards. As part of a x4 PCI Express high-speed flash memory module, developed by the Computer Architecture Group, the resulting hardware design was put to operation on a Lattice programmable logic device and allowed for low latency direct memory access operations with bandwidths close to 800 MBps. The thesis comprises a detailed description of the development environment, the resulting hardware and an analysis of performance and portability to various FPGA technologies. Appropriate verification strategies for a bridge type device are described and the results evaluated. Finally, the design flow for Lattice Semiconductor programmable logic devices is described and optimization and fine-tuning strategies are given with rescpect to the ultimate goal of timing closure.


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