Ruprecht-Karls-Universität Heidelberg


Design and Implementation of Enhanced Features for FSMDesigner 4 with Complex HDL Generation Options

Diploma Thesis by Matthaeus Peterson

Abstract:

The growing complexity of hardware makes it desirable to use a tool to design hardware on a higher level of abstraction. Finite State Machines are an ideal way to define circuits that control data paths or other hardware. FSMDesigner 4 allows the user to construct state machines with a Graphical User Interface. This program has the ability to export FSMs into a text based Verilog or VHDL file. The aim of this thesis was to achieve three goals. Porting FSMDesigner 4 to the current crossplatform library Qt 4, implementation of new features including functional tests to guarantee the reliability of FSMDesigner 4 and a mechanism for automatic generation of fault tolerant Finite State Machines. The programming of FSMDesigner was performed modular and pattern based to allow effortless maintainability of the code. The newly implemented functions increase the usability of FSMDesigner and enable a more intuitive way of designing FSMs. On FPGAs which are errorprone due to bit flips in registers through high energy radiation it is desirable to have state machines which work correctly despite of an erroneous change in its register. In this thesis an algorithm was proposed and implemented which generates such a kind of FSMs.

 

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