Ruprecht-Karls-Universität Heidelberg

Exploring the Testability Methodology and the Development of Test and Debug Functions for a Complex Network ASIC

Diploma Thesis by Markus Mueller


In this diploma thesis the design for testability (DFT) approach for a modern application specific integrated circuit (ASIC), namely the Extoll network chip, is explored.

Therefore, after analyzing today’s ASIC testability methodologies like scandesign, JTAG boundary scan and memory built-in self-test, the whole DFT flow from scan insertion to vector generation for wafer test, was tested on parts of the Extoll design using state of the art EDA tools.

Additionally a module, called the Debug Port, which enables debugging of the Extoll ASIC during bring-up, by providing access to the Extoll register file over I2C and SPI, was developed, implemented and verified using the Verilog HDL and Open Verification Methodology (OVM).


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