Ruprecht-Karls-Universität Heidelberg


Master Theses Overview

  • Manuel Abele (Supervisor: Ulrich Brüning, Mondrian Nüssle [extern]) [MScTI_THESIS] 
    Concept and Prototype for a Global Collective Engine to Offload Nonblocking Collective
    Computation Operations in MPI
     [Abstract]
  • Niels Buwen (Supervisor: Sarah Neuwirth) [IMa]
    Design and Implementation of a Transport Layer for the Extoll Network Interface in the
    BrainScaleS Neuromorphic Computing Platform [Abstract]
  • Eduard Fast (Supervisor: Tobias Markus) [MScTI_THESIS] 
    Design and modeling of a high-efficient single-phase PFC-Rectifier Power-Supply [Abstract]
  • Fabian Finkeldey (Supervisor: Markus Müller) [MScTI_THESIS] 
    Implementation of a High Speed Pipelined Microcode Engine [Abstract]
  • Tobias Groschup (Supervisor: Sarah Neuwirth) [IMa] 
    Implementation and Evaluation of a Parallel Distributed File System for the EXTOLL
    High-Performance Network
    [Abstract]
  • Abdulhamid Han (Supervisor: Ulrich Brüning) [MScTI_THESIS] 
    Messung und Analyse von U/I Kennlinien integrierter Schaltungen [Abstract]
  • Alexander Jäger (Supervisor: Juri Schmidt) [MScTI_THESIS] 
    Exploration and Evaluation of State of the Art Interfaces used in FPGAs [Abstract]
  • Felix Kaiser (Supervisor: Stefan Kosnac) [MScTI_THESIS] 
    Design and Verification of a RISC-V Conform, Double-Precision Fused Multiply-Add Unit [Abstract]
  • Stefan Kosnac (Supervisor: Markus Müller, Maximilian Thürmer) [MScTI_THESIS] 
    Design Aspects of a Decision Feedback Equalizer in a 28nm Technology [Abstract]
  • Daniel Kruck (Supervisor: Niels Burkhardt) [MScTI_THESIS] 
    Simulating and Analyzing the Extoll Network with a Timing-Accurate SystemC Model [Abstract]
  • Ingo Kunkel (Supervisor: Niels Burkhardt) [MScTI_THESIS]
    Development of an IDE for the e Verification Language based on IntelliJ IDEA [Abstract]
  • Martin Lingnau (Supervisor: Sarah Neuwirth, Dirk Frey) [MScTI_THESIS] 
    Traversal Algorithms for Ray Tracing - An Architectural Evaluation [Abstract]
  • Michael Magin (Supervisor: Markus Müller) [MScTI_THESIS]
    Signal and Power Analysis of a High Performance ASIC Package [Abstract]
  • Tobias Markus (Supervisor: Markus Müller) [MScTI_THESIS] 
    High-Speed Clock Generation Architecture for a Multi-Rate SerDes in 28nm [Abstract]
  • Thomas Ott (Supervisor: Sarah Neuwirth) [MScTI_THESIS] 
    Multi-GPU Support for the Network-Attached Accelerators Approach [Abstract]
  • Philipp Schäfer (Supervisor: Frank Lemke) [MScTI_THESIS] 
    Design and Implementation of a Prototype ASIC for a Unified DAQ Interconnection Network [Abstract]
  • Juri Schmidt (Supervisor: Myles Watson) [MScTI_THESIS] 
    A Hybrid Memory Cube Controller for FPGAs [Abstract]
  • Tobias Thommes (Supervisor: Juri Schmidt) [MScTI_THESIS] 
    Design and Implementation of an EXTOLL Network-Interface for the Communication FPGA
    in the BrainScaleS Neuromorphic Computing System
     [Abstract]
  • Martin Wenzel (Supervisor: Niels Burkhardt) [MScTI_THESIS] 
    An Extendable Environment for Control and Status Register File Generation [Abstract]
  • Sebastian Wittka (Supervisor: Niels Burkhardt) [MScTI_THESIS] 
    Functional Verification of a Microcode Engine using the Universal Verification Methodology [Abstract]
  • Felix Zahn (Supervisor: Richard Leys) [MScTI_THESIS] 
    Development of a Flexible Management Software Environment for the EXTOLL Network [Abstract]
  • Julian Zeilfelder (Supervisor: Niels Burkhardt) [IMa] 
    A New Tool for Efficient Design and Checking of Finite State Machines [Abstract]
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