Ruprecht-Karls-Universität Heidelberg

Master Theses Overview

  • [MScTI_THESIS] Manuel Abele (Supervisor: Ulrich Brüning, Mondrian Nüssle [extern])
    Concept and Prototype for a Global Collective Engine to Offload Nonblocking Collective
    Computation Operations in MPI
  • [MScTI_THESIS] Eduard Fast (Supervisor: Tobias Markus)
    Design and modeling of a high-efficient single-phase PFC-Rectifier Power-Supply [Abstract]
  • [MScTI_THESIS] Fabian Finkeldey (Supervisor: Markus Müller)
    Implementation of a High Speed Pipelined Microcode Engine [Abstract]
  • [IMa] Tobias Groschup (Supervisor: Sarah Neuwirth)
    Implementation and Evaluation of a Parallel Distributed File System for the EXTOLL
    High-Performance Network
  • [MScTI_THESIS] Abdulhamid Han (Supervisor: Ulrich Brüning)
    Messung und Analyse von U/I Kennlinien integrierter Schaltungen [Abstract]
  • [MScTI_THESIS] Alexander Jäger (Supervisor: Juri Schmidt)
    Exploration and Evaluation of State of the Art Interfaces used in FPGAs [Abstract]
  • [MScTI_THESIS] Felix Kaiser (Supervisor: Stefan Kosnac)
    Design and Verification of a RISC-V Conform, Double-Precision Fused Multiply-Add Unit [Abstract]
  • [MScTI_THESIS] Stefan Kosnac (Supervisor: Markus Müller, Maximilian Thürmer)
    Design Aspects of a Decision Feedback Equalizer in a 28nm Technology [Abstract]
  • [MScTI_THESIS] Daniel Kruck (Supervisor: Niels Burkhardt)
    Simulating and Analyzing the Extoll Network with a Timing-Accurate SystemC Model [Abstract]
  • [MScTI_THESIS] Ingo Kunkel (Supervisor: Niels Burkhardt)
    Development of an IDE for the e Verification Language based on IntelliJ IDEA [Abstract]
  • [MScTI_THESIS] Martin Lingnau (Supervisor: Sarah Neuwirth, Dirk Frey)
    Traversal Algorithms for Ray Tracing - An Architectural Evaluation [Abstract]
  • [MScTI_THESIS] Michael Magin (Supervisor: Markus Müller)
    Signal and Power Analysis of a High Performance ASIC Package [Abstract]
  • [MScTI_THESIS] Tobias Markus (Supervisor: Markus Müller)
    High-Speed Clock Generation Architecture for a Multi-Rate SerDes in 28nm [Abstract]
  • [MScTI_THESIS] Philipp Schäfer (Supervisor: Frank Lemke)
    Design and Implementation of a Prototype ASIC for a Unified DAQ Interconnection Network [Abstract]
  • [MScTI_THESIS] Juri Schmidt (Supervisor: Myles Watson)
    A Hybrid Memory Cube Controller for FPGAs [Abstract]
  • [MScTI_THESIS] Tobias Thommes (Supervisor: Juri Schmidt)
    Design and Implementation of an EXTOLL Network-Interface for the Communication FPGA
    in the BrainScaleS Neuromorphic Computing System
  • [MScTI_THESIS] Martin Wenzel (Supervisor: Niels Burkhardt)
    An Extendable Environment for Control and Status Register File Generation [Abstract]
  • [MScTI_THESIS] Sebastian Wittka (Supervisor: Niels Burkhardt)
    Functional Verification of a Microcode Engine using the Universal Verification Methodology [Abstract]
  • [MScTI_THESIS] Felix Zahn (Supervisor: Richard Leys)
    Development of a Flexible Management Software Environment for the EXTOLL Network [Abstract]
  • [IMa] Julian Zeilfelder (Supervisor: Niels Burkhardt)
    A New Tool for Efficient Design and Checking of Finite State Machines [Abstract]
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