Ruprecht-Karls-Universität Heidelberg

A Hybrid Memory Cube Controller for FPGAs

Master Thesis by Juri Schmidt


During the last decades, the computational power of microprocessors has steadily improved. Unfortunately, the processor speedup was substantially larger than for memory. Hence, memory has become the ’bottleneck’ of high-performance systems. Furthermore the impact of high clock frequencies on power consumption has been underestimated. The two biggest issues engineers face with regard to high-performance computing are the memory wall and the power wall. To overcome these issues, new architectural solutions must be developed.

The main goal of this thesis is to implement a parameterizable memory controller for a Hybrid Memory Cube. The target application is a bandwidth-optimized receiving endpoint for an image-processing application, which requires an effective bandwidth of at least 8GB/s. Before the implementation of the memory controller is presented, DRAM technology and common memory interfaces that use DRAM cells are introduced. In the next step, the Hybrid Memory Cube memory architecture, which promises significant improvement with regard to bandwidth and efficiency, is presented. The development of the memory controller is described starting from the main architectural concept of the internal functional units, which are mainly a transmit and a receive block. These functional units can be fully adapted to different system environments using parameters. Next, the implementation of the specific features such as CRC checks and link retries is presented. Finally, the memory controller is simulated.


« back

back to top