Ruprecht-Karls-Universität Heidelberg


Design and Implementation of a Prototype ASIC for a Unified DAQ Interconnection Network

Master Thesis by Philipp Schaefer

Abstract:

Particle physics, also called high energy physics, is a branch of physics which studies the elementary constituents of matter and radiation. As particle physics of former times were limited to molecules, atoms, and nucleons, today's particle physicists focus on elementary particles such as quarks, leptons, photons, gluons, and bosons. Modern physical models are often proved with colliding-beam experiments performed with particle colliders. As the complexity of these experiments increases, the amount of aggregated data proportional to time gets bigger. This data is produced by thousands of front-end electronics which have to be read out in parallel. Hence, efficient data acquisition networks are required which provide high bandwidth to cope with these big amounts of data. Furthermore, these networks require a fine granular timing distribution system to synchronize all parts of the network. This is necessary to assign the incoming data to its particular front-end electronic.

The CBM experiment at the Facility of Antiproton and Ion Research in Darmstadt was designed to answer questions about the origin of mass in our universe. It is planned to create quark gluon plasma which existed for a short time, fractions of seconds after the big bang. A data acquisition network for this experiment was developed by the Chair of Computer Architecture at the Institute of Computer Engineering at the University of Heidelberg. Its main feature is that data acquisition, network control, and timing distribution is implemented via one bidirectional fiber link while delivering high bandwidth for efficient data acquisition.

This master thesis focusses on the digital part of a chip developed for the CBM network. The chip gathers and bundles data aggregated by the front-end electronics and sends it back to the Back-End. In the course of the thesis, a prototype was designed, implemented, and tested on FPGA and in simulation. The front-end and back-end design flow and the testing of the digital part of the chip will be described and explained.

 

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