Ruprecht-Karls-Universität Heidelberg


High-Speed Clock Generation Architecture for a Multi-Rate SerDes in 28 nm

Master Thesis by Tobias Markus

Abstract:

A clock generation architecture based on Injection Lock Ring Oscillator for quadrature phase generation and low phase noise is proposed in this work. The Injection Lock Ring Oscillator is designed for a 28 nm technology on the schematic level. The design approaches and methodology is described in detail in this work.

The tuning range of the ILRO from 8 to 12.5 GHz is reached at every process corner. A phase noise about -110 dBc/Hz @1MHz was reached. The supply voltage used is 850 mV.

 

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