Ruprecht-Karls-Universität Heidelberg

Design Aspects of a Decision Feedback Equalizer in a 28 nm Technology

Master Thesis by Stefan Kosnac


With increasing computing power of microprocessors the demand for high speed data transmission is growing. Although in principle, the data bandwidth can be directly increased by using a larger number of parallel channels, this is not feasible due to the limited number of pins available. Therefore, inter-chip communication on printed circuit boards (PCBs) or through cables uses serializers to transmit all data with a single channel. As a consequence higher data-rates are necessary, which raise the requirements for transmitter and receiver. The frequency dependent attenuation of the signal causes intersymbol interference (ISI). An efficient method to remove ISI at the receiver is the use of a decision feedback equalizer (DFE). The ISI on the current symbol caused by previously received symbols is removed by feeding back a weighted version of the previous received symbols matching the channel response. This work presents and compares different DFE architectures, especially the summation circuits are considered, which add the received signal to the feedback. Finally, the implementation of a 5-tap quarter-rate DFE in an existing serializer project is reported.


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