Ruprecht-Karls-Universität Heidelberg

Implementation of a High Speed Pipelined Microcode Engine

Master Thesis by Fabian Finkeldey


This master’s thesis revisits the concept of microprogramming in the context of replacing hardwired control-circuitry with a programmable and highly flexible microcode engine. The design developed and implemented in this work is aimed to perform general purpose control-tasks, in an environment, where the requirements are not fully known or might change over time.

The challenges of this task are approached with the concept of microprogramming and elements from high-performance processors. With a dedicated instruction-memory, implemented as an SRAM, a simple micro-sequencer and a one-instruction-per-cycle performance, the basic design-elements of a conventional microcode engine are used. Extended with a custom instruction-set-architecture, a five-stage pipeline and an execution unit, including a load/store-unit and an arithmetic-logic-unit, the functionality is increased towards a RISC-processor.

Being placed between hardwired circuitry and advanced processors, the microcode engines behaviour is determined by a program. To efficiently use it, the means to generate machine code from a programming language are required. Therefore, an assembler-language for the custom instruction-set is defined to increase the abstraction-level of the program slightly above the hardware-layer. To generate binary machine-code, an assembler is also implemented and presented in this work.


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