Ruprecht-Karls-Universität Heidelberg


A New Tool for Efficient Design and Checking of Finite State Machines

Master Thesis by Julian Zeilfelder

Abstract:

Due to the increasing complexity of modern hardware, new software tools are required in order to facilitate their design on a higher level of abstraction. Thereby, the efficiency of the hardware design process is increased and the software tools further assist in achieving the required correctness. Especially digital sequential circuits represented by finite state machines have become essential in the design of modern digital systems. For this reason, the present master thesis describes the development of a new tool for efficient design and checking of finite state machines.

The presented software tool provides a modern graphical user interface including the standard features such as saving and loading projects. A special drawing area is supplied in order to allow for the graphical design of finite state machines. Besides states and transitions, multiple other elements as hyper transitions, joins and links were implemented to enable a clear overview of the scene. Furthermore, a table representation of the output and input values allows for their easy editing. In addition, several checks for states and transitions were implemented to ensure accurate state machines. Finally, a feature to convert the designed finite state machines into the hardware description language Verilog is provided.

To realize this tool the application framework JavaFX was utilized, which allows for the creation of modern graphical user interfaces. Furthermore, the software design pattern Model-View-ViewModel is applied to gain a clear separation of the view and the underlying data model. In the end, the result of the presented work is a stable, well-structured and user-friendly software tool.

 

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