Ruprecht-Karls-Universität Heidelberg

Design and Verification of a RISC-V Conform, Double-Precision Fused Multiply-Add Unit

Master Thesis by Felix Kaiser


With the rise of RISC-V, an extensible and open source Instruction Set Architecture, computer architecture obtains the opportunity for a new golden age. Though the new RISC architecture hasn't found its way into High-Performance Computing. As one of the crucial metrics for computing clusters constitute the floating-point operations per second, highly optimized floating-point units are essential. This work presents the development of a RISC-V-compliant, so called fused multiply-add unit, that is able to perform one multiplication combined with an addition per clock cycle. It covers, inter alia, the efficient processing of the wide datapaths of 64-bit units. The second part of this work focusses on the underestimated, though not less important topic of verification. To handle the huge amount of possible inputs, a simulation-based approach, applying the industry standard Universal Verification Methodology, is implemented. UVMs purpose is to keep the verification components reusable and modular, so that they can be used within different verification hierarchy levels. A special feature of the proposed environment represents the usage of two "known-good" reference models, of which one is the FPU of the Intel processor the testbench runs on.


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