Ruprecht-Karls-Universität Heidelberg

Investigation of the Capabilities of SystemC

Project Report by Daniel Kruck


SystemC is well respected for its capabilities to model hardware at higher levels of abstraction. In this practical course, the language features are explored. Especially, the TLM-2.0 standard as part of SystemC is analyzed for its high level techniques. Based on the observations, a crossbar model is developed. Even though the crossbar model utilizes several TLM-2.0 classes, the model itself is not TLM-2.0 compliant. The reason for this is that TLM-2.0 is designed for memory-mapped buses, but the crossbar model rather requires some sort of pipelined transaction protocol. However, the latest version of the model outperforms the Verilog/SystemVerilog model with respect of execution speed up to 300 times. Note that the reported speedup can be improved even further by small changes in the present code or by the usage of a hand-tailored library.


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