Ruprecht-Karls-Universität Heidelberg

Verilog-AMS Model of a Mueller Muller CDR

Project Report by Tobias Markus


In this work a reusable Verilog-AMS module for a Clock Data Recovery based on the Mueller Mueller Phase Detector was implemented. The model is configurable to evaluate different parameters. Digital blocks in the model are written in synthesizable Verilog.

The second part of this report is the evaluation of the implemented concept. The transfer function of the Mueller Mueller Phase Detector, the step function for the closed loop CDR was simulated and a jitter tolerance analysis was done.


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