Ruprecht-Karls-Universität Heidelberg

Characterization of 7- and 8T Dual-Port SRAM Cells in Respect of Their Maximum Speed in 28nm HPP

Project Report by Manuel Abele


In this work, a 7- and 8T dual-port SRAM bitcell with di erent readout methods are analyzed and compared regarding their reading and writing speed, the stability to maintain their state and their power consumption. In the theoretical part, the fundamental principles for the reading and writing procedure as well as the speed of a CMOS inverter are considered. It can be shown that a boost voltage is necessary to run a 7T cell and that the maximum speed is proportional to the supply voltage and antiproportional to the device size.

A simulatory part complements the results of SPICE simulations for reading and writing scenarios, asymmetrical inverters and decreased inverter supply voltage. It is found out that both the 7- and 8T setup can be run using minimum-sized devices and a reduced inverter voltage, making an additional boost voltage exceeding Vdd unnecessary. The 7T setup is more energy ecient and capable of reaching a speed of only just 1:5 GHz for an inverter voltage between 490 and 650mV, while the 8T cell can theoretically be run even faster, however being a higher load for the control logic.


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