Ruprecht-Karls-Universität Heidelberg


Synchronous SRAM Based FIFO With Minimum Latency of Once Clock Cycle for High Frequencies

Project Report by Tobias Thommes

Abstract:

In this work, a FIFO design is developed which provides high speed write- and readout-cycles with a latency of only one single clock cycle.

In the first part of this work, the architecture for this fast FIFO design is described. The different parts of the design will be discussed in detail. With some adaptations, the proposed design can also become an asynchronous FIFO with two independent read- and write-clocks. This will be shortly treated at the end of this work.

In the second part, the practical implementation of the design will be considered. It will be explained that for synthesis reasons, concerning the design thoughts from the first part, it is necessary to build a structural HDL description rather than a functional one. For the SRAM, on witch the FIFO will be based, the 7T-cell designed by Manuel Abele will be used.

 

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